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VF910User'sManual
ffi
Devices,
RealTime
Inc.
ISO9001 and AS9100 Certified
Publication
No.910-95508
r Tr;lft{
A
Y.[ 7IU
User'sManual
ffi
INC.
REALTIMEDEVICES,
PostOfficeBox906
16804
StateCollege,Pennsylvania
Phone:@14)234-8A87
FAX:(814)234-5218
Publishedby
RealTimeDevices,Inc.
P.O.Box 906
StateCollege,PA 168(X
Copyright@ 1994by RealTime Devices,Inc.
All rightsreserved
Printedin U.S.A.
Rev.B 9550
Tableof Contents
INTRODUCTION......
,i-1
Application
CHAPTER 1 - BOARD SETTINGS
...............
l-3
Factory-ConfiguredSwitch and JumperSettings
.............1-4
P3 - User Timer/CounterOutput Select(FactorySetting:P2-43:TRIG, P2-44:OT0)
1-4
P4 - User Timer/CounterClock Source(FactorySettings:CLKO-OSC,CLK1-OT0, CLK2-OTl) ..............
l-5
....................
P5 - UserTimer/CounterGateSource(FactorySettings:All Gates:+5V) ...........
...........1-6
P6 - Single-Ended/Differential
Analog Inputs (FactorySetting: S (16 Single-Ended))
............1-6
P7 - Analog Input Voltage Rangeand Polarity (FactorySetting:5V, BI (12.5 Volts))
........1-6
P8 - DAC I OutputVoltageRange(FactorySetting:+5 to -5 volts) ...........
........1-7
P9 - DAC 2 Output Voltage Range(FactorySetting:+5 to -5 volts) ...........
..............
l-8
Sl - BaseAddress(FactorySetting:300 hex (768decimal)).................
............1-9
52 - DifferentiaVSingle-Ended
Ground Switch (FactorySetting:OPEN)
.............1-9
Resistorson Digital VO Lines
Pull-up/Pull-down
CHAPTER 2 - BOARD INSTALLATION......
Connectingthe Analog Input Pins
Boards
Connectingthe TriggerIn andTriggerOut Pins,Cascading
andDigital I/O ...............
Connectingthe Timer/Counters
Runningthe 9I0DIAG DiagnosticsProgram
CHAPTER 3 - HARDWARE DESCRrPTrON...........
Digital VO, ProgrammablePeripheralInterface
2-l
............2-4
.......................2-6
..................2-6
.....................2-6
.............3-1
.................3-5
CHAPTER 4 - BOARD OPERATIONAND PROGRAMMING
ContinuousConvertMode ..,........
.............4.1
........4-8
User-Available 8254
BA + 0: A/D DataLow Byte (ReadOnly)
BA+ l: A/DDataMiddleByte(ReadOnly)...........
BA + 2: A,/DDataHigh Byte (ReadOnly)
BA + 3: Board ReadylClear20-bit ConversionCounter(Read/Write)
BA + 4: 8254Timer/Counter
0 (Read/lVrite)
BA + 5: 8254Timer/Counter
1 (ReadAVrite)
BA + 6: 8254Timer/Counter2 (Read/TVrite)
BA + 7: 8254ControlWord (Write Only)...........
BA + 8: PPI Port A - Digital VO (Read/lVrite)..............
BA + 9: PPI Port B - ChanneVGainSelect(ReadAilrite)
BA + l0: PPI Port C - Digital VO (ReadAVrite).............
BA + 7: 8255PPI ControlWord (Write Only) ...........
BA + 12: D/A Converter I LSB (Read/Write)
BA + 13: D/A ConverterI MSB (Read/tlVrite)
BA + 14: D/A Converter2 LSB (Read/lVrite)
BA + 15: D/A Converter2 MSB (Read/Write)
BA + 16: User 8254Timer/Counter0 (ReadAMrite)..............
BA + 17: User 8254Timer/CounterI (Read/Write)...............
BA + l8: User 8254Timer/Counter
2 (ReadAVrite)..............
BA + 19: User 8254ControlWord (Write Only) ...........
BA + 20: BoardSetupRegister(Write Only) ...........
BA + 2l: A/D TriggerMode Register(Write Only) ...........
BA +22: ResetAJpdate
DACs (Read/lVrite)...............
.................4-15
...4-15
.................4-15
................4-15
.............4-15
.............4-16
.............4-16
.......4-16
...............4-16
..............4-16
...............4-17
.....................4-17
............4-19
...........4-19
............4-19
..........4-19
..........4-19
.........4-19
..........4-19
.................4-20
.......................4-20
.............4-21
....................4-21
CHAPTER 5 - CALCULATING FREQUENCIES,VOLTAGES,AND BITS .............................5-l
Calculatingthe Settingsfor the 8254Timer..
ConversionResultsand CorrectionFactor
Input Voltagesand Output Frequencies
.....................5-3
.........................5-7
........5-8
CHAPTER 6 _ CALIBRATION
......6-l
APPENDIXA - VF9TOSPECIFICATIONS
APPENDIXB _P2 CONNECTORPIN ASSIGNMENTS
APPENDIX C _ COMPONENTDATA SHEETS
APPENDIXD-WARRANTY
...A-1
B-l
....................C.1
.............D.1
ut
List of Illustrations
1t
l - l
BoardLayout ShowingFactory-Configured
Settings...................
t-2
UserTimer/CounterOutputSelectJumpers,P3 ...........
_t-J
UserTimer/CounterClock SourceJumpers,P4 ................
1A
i-a
82l4Timer/CounterCircuitBlock Diagram.................
User Timer/CounterGateSourceJumpers,P5 ................
l-5
l-6
t-7
1-8
1-9
1-10
t-l I
1-12
1-13
t-14
a!
z-l
., .,
2-3
2-4
2-5
3-l
3-2
J-J
4-l
4-2
4-3
4-4
4-5
4-6
6-1
Single-Ended/Differential
AnalogInput SignalType Jumpers,P6.............
Analog Input VoltageRangeand Polarity,P7 ................
l-3
..................
.............1-4
........1-4
............1-5
..........1-5
........................1-6
DAC I OutputVoltageRangeJumper,P8 .............
...........1-6
...................1-7
DAC 2 OutputVoltageRangeJumper,P9 .............
B a s eA d d r e s sS w i t c h ,S l . . . . . . . . . . . . . . . .
......................1-8
Differential/Single-Ended
GroundSwitch,52 ................
Adding Pull-upsand Pull-downsto Digital VO Lines
Gain Circuitryand Formulafor CalculatingGm ...........
Diagramfor Removalof SolderShort............
P 2 U O C o n n e c t oPr i n A s s i g n m e n t.s. . . . . . . . . . . . . .
Single-Ended
Input Connections............
with DedicatedGroundsInput Connections............
Single-Ended
DifferentialInput Connections............
CascadingTwo Boardsfor Simultaneous
Sampling
V F 9 l 0 B l o c kD i a g r a m
V/F Timing and CountingBlock Diagram.................
User 8254Timer/CounterCircuitry
SingleConvertMode Timing Diagram
SingleConvertMode Flow Diagram
ContinuousConvertMode Timing Diagram
ContinuousConvertMode Flow Diagram
CascadedBoards,Single ConvertMode Flow Diagram
User 8254Timer/CounterCircuitry
...................1-7
..........1-9
.............1-10
1-l I
..........
....1-l I
......2-3
..............2-4
................2-5
.................2-5
.................2-6
.....................3-3
...............3-4
......................3-6
...............4-6
....................4-1
........4-8
...........4-9
.........4-10
....................4-13
INTRODUCTION
t-z
The VF9l0 variable resolution integrating analog VO board turns your IBM PCD(T/AT or compatible computer
into a high-performancedata acquisitionand control system.Installedwithin a single shortor full-size expansion
slot in the computer,the VF9l0 features:
.
.
.
.
.
.
.
.
.
.
.
.
.
8 differential,8 single-endedwith dedicatedgrounds,or 16 single-endedanaloginput channels,
Resolution to l8 bits using a synchronousvoltage-to-frequencyconverter,
0 to +5, 0 to +10, !2.5, or t5 volt input range,
Progtammablegainsof 1,2,4, and 8 with an on-boardgain multiplier circuit,
Clock controlled A./D conversion,
l6-bit samplecounter,
Software selectablesystem clock, interrupt sourceand intenupt channel,
Trigger in and trigger out for external triggering or cascadingboards,
Two l2-bit analog output channels,
+5, tl0, 0 to +5, or 0 to +10 volt analogoutputrange,
Three user available 16-bit timer/counters,
16 8255-basedTTL/CMOS compatibledigital VO lines,
+5 volt operation.
The following paragraphsbriefly describethe major functions of the board. More detailed discussionsof board
functions are included in Chapter 3, Hardware Description, and Chapter4, Board Operation and Programming.The
board setupis describedin Chapterl, Board Settings.
Analog-to-DigitalConversion
The analog-to-digital (A/D) conversion circuitry receivesup to eight differential, eight single-endedwith
dedicated grounds, or 16 single-endedanalog inputs and converts theseinputs into frequencies.The frequenciesare
representedby 20-bit plus overflow words (in 3 x 8-bit forma0 which are read and/or transferredto PC memory.
An on-board headerconnector lets you jumper the inputs for differential or single-endedoperation. When in the
differential mode, the analog input channelscan be individually set for single-endedor differential operation by
configuring DIP switch 52. This feature lets you mix single-endedand differential input channels.Two unipolar and
two bipolar rangescan be selected:0 to +5, 0 to +10, +2.5, or +5 volts. The rangeis customerspecifiedwhen
ordering the board, and the board is calibrated for the selectedrange. Software programmable gains of 1,2,4, and 8
with an on-board gain multiplier circuitry let you customize the input range.
A./D conversions are performed by a voltage-to-frequency(V/F) converter. This exceptionally accurateconverter technology lets you vary the resolution of your conversion while maintaining the full input voltage range.
Instead, you trade speedfor precision. For example, with a I MHz system clock and the input range set for 5 volts,
lO-bit conversionsare performedat a rate of 488 samplesper secondswith a resolutionof 4.88 millivolts, l2-bit
conversions are performed at a rate of 122 samplesper secondwith a resolution of I .22 millivolts, and 18-bit
conversions are performed at a rate of 2 samplesper secondwith a resolution of 19 microvolts.
The converted data is read and/or transferredto PC memory, one byte at a time, through the PC data bus.
Digital-to-AnalogConversion
The digital-to-analog (D/A) circuitry featurestwo independentl2-bit analog output channelswith individually
jumper-selectableoutput rangesof -5 to +5 volts, -10 to +10 volts, 0 to +5 volts, or 0 to +10 volts. Data is programmed into the D/A converter by writing two 8-bit words, the LSB and the MSB. Both outputs can be simultaneously updated by writing to an VO port.
Digital VO
The VF9l0 has 16 TTUCMOS compatible digital VO lines which can be directly interfaced with external
devices or signals to senseswitch closures,trigger digital events,or activate solid-staterelays. These lines are
provided by the 8255 programmableperipheral interface (PPI). Padsfor installing and activating pull-up/pull-down
resistors are included on the board. Installation proceduresare given near the end of Chapter I, Board Settings.
i-3
What ComesWith Your Board
You receivethe following items in your VF9l0 package:
.
'
.
.
VF910 interfaceboard
Softwareand diagnosticsdiskettewith exampleprogramsin BASIC, Pascal,and C sourcecode
rtdlinx TSR DOS driver
User's manual
If any item is missingor damaged,pleasecall Real Time Devices' CustomerServiceDepartmentat
(814) 234-8087.If you requireserviceoutsidethe U.S., contactyour local distributor.
Board Accessories
In addition to the items includedin your VF9l0 package,Real Time Devicesoffers a fult line of softwareand
hardwareaccessories.
Call your local distributoror our main office for more informationabout theseaccessories
and
for help in choosing the best items to support your board's application.
Application Software and Drivers
Our custom applicationsoftwarepackagesprovide excellentdataacquisitionand analysissupport.Use
SIGNAL*VIEW for monitoring and data acquisition, or SIGNAL*MATH for integrateddata acquisition and
sophisticateddigital signalprocessingand analysis.rtdlinx (includedwith your board)and rtdlinxAlB drivers
provide full-featured high level interfacesbetweenthe board and custom or third party software, including Labtech
Notebook, NotebookD(E, and LTlControl. rtdlinx sourcecode is available for a one-time fee.
Hardware Accessories
Hardwareaccessories
for the VF9l0 includethe TMX32 analoginput expansionboardwith thermocouple
compensationwhich can expanda singleinput channelon your boardto I 6 differentialor 32 single-endedinput
channels,MR seriesmechanicalrelay output boards,OP seriesoptoisolateddigital input boards,the OR16 mechanical relay/optoisolateddigital UO board,the USF8 universalsensorfront-endwith sensorexcitation,the TB50
terminal board and XB50 prototype/terminal board for prototype developmentand easy signal access,the EX-XT
extender board for simplified testing and debuggingof prototype circuitry, and the XT50 twisted pair ribbon cable
assemblyfor external interfacing.
Using This Manual
This manualis intendedto help you install your new boardand get it running quickly, while also providing
enough detail about the board and its functions so that you can enjoy maximum use of its featureseven in the most
complex applications.We assumethat you alreadyhavean understandingof dataacquisitionprinciplesand that you
can customize the example software or write your own applicationsprograms.
When You Need Help
This manual and the example programs in the software packageincluded with your board provide enough
information to properly use all of the board's features.If you have any problemsinstallingor using this board,
contactour TechnicalSupportDepartment,(814) 234-8087,during regularbusinesshours,easternsrandardtime or
easterndaylight time, or senda FAX requestingassistance
to (814) 234-5218.When sendinga FAX request,please
include your company'sname and address,your name,your telephonenumber,and a brief descriptionof the
problem.
i-4
CHAPTER 1
BOARD SETTINGS
The VF910 boardhasjumper and switch settingsyou can
changeif necessaryfor your application.The boardis factoryconfigured as listed in the table and shown on a diagramin the
beginningof this chapter.Shouldyou needto changethesesettings, usetheseeasy-to-followinstructionsbeforeyou install the
board in your computer.
Note that by installing resistorpacks at three locations around
pads,you can
the 8255 PPI and solderingjumpers in the associated
configurethe 16 availabledigital VO lines to be pulled up or pulled
down. This procedureis explainednear the end of this chapter.
Also note that by installingresistivecomponents,you can add
your own gain multiplier for the softwareprogrammablebinary
gainsof I,2,4, and 8. The gain multiplier circuitry is describedat
the end of this chapter.
l-l
t-2
Factory-ConfiguredSwitchand Jumper Settings
Table l-1 lists the factory settingsof the user-configurable
switch andjumpers on the VF9l0 board.Figure t - l
showsthe board layout and the locationsof the factory-setjumpers.The following paragraphsexplain how to
changethe factory settings.
Table1-1- FactorySettings
Switch/
Jumper
FunctionControlled
FactorySetting
Setsthe usertimer/counter
outputsignalsavailable
alP2-43 andP2-44
P2-43:TRIG,P2-44:OUTO
DE
P4
CLKO:
OSC,CLK1:OT0,
Setsthe clocksourceslor the usertimer/counters CLK2:OT1(cascaded)
P5
+5V,GATE1:+5V,
GATEO:
Setsthegatesourcesfor the usertimer/counters GATE2:+5V
P6
Setsthe analoginputsas 16single-ended
or 8
single-ended
withGND/8differential;
usedwith52
(3 jumpers
16single-ended
installed
on S pins)
P7
Setstheanaloginputvoltagerangeandpolarity
5V,Bl (-2.5to +2.5volts)
P8
Setsthe D/A outputvoltagerangetor DAC1
t5, X1 (-5to +5 volts)
P9
Setsthe D/A outputvoltagerangefor DAC2
15,X1 (-5to +5 volts)
S1
Setsthe baseaddress
300 hex(768decimal)
DZ
Connectsthe negativeside of differentialinputsto
ground for 8 single-endedwith ground operation
OPEN (16 single-ended)
oooo
oooooo
oll r
oo
OOa2c51OO
oooooo
oooo
ooooooooo
ooooooooooo
oo
oo
a-renl
PAL
!$
33
oooooo
oooooooo
oo
oo
oEr
oo
oo azcssoo
oo
oo
oooooooo
oooooo
trOr
OO
oo
oo
oo
oo
oo
oo
ooooooooooo
ooooooooo
Fig.1-1- BoardLayoutShowingFactory-Configured
Settings
l-3
P3 -
user Timer/counter output Select (Factory setting: P2-432TRIG, p2.44: or0)
This headerconnector,shown in Figure I -2, lets you selectone of two signalsto be presentat eachof two of the
P2 UO connectorpins, P2-43 andP2-44.This allows you more flexibility when settingup the board.P2-43 can be
configuredto provide an externaltrigger (TRIG) or the outputof usertimer/counter2 (OT2).P2-44 canbe configured to provide the output of usertim6r/counter0 (OT0) orthe outputof usertimer/counterI (OTl). Nore that when
you cascademultiple boards,you must configureP2-43to cary the externaltrigger signal (TRIG) on eachboard
that outputsa trigger to the next boardin the chain.
TRIG
II
oT2
oT0
oT1
Fig.1-2 P4 -
User Timer/CounterOutput Select Jumpers, P3
User Timer/Counter Clock Source (Factory Settings: CLK0-OSC, CLKI-OTO, CLK2-OTf )
This headerconnector,shown in Figure l-3, lets you selectthe clock sourcesfor the user available 8254 timerl
counters,TC0, TCl, and TC2. The factory setting cascadesall three timer/counters,with the clock sourcefor TCO
being the on-board2MHz oscillator,the output of TCOproviding the clock for TCl, and the output of TCI providing the clock for TC2. You can connectany or all of the sourcesto either of two externalclock inputs (the first
source labeled ECI on the headerand EXT CLKI at P2-41, andthe secondsourcelabeled EC2 on the headerand
EXT CLK2 atP2-45),or you can setTCl and TC2 to be clockedby the 2 MHz oscillator.Figure l-4 showsa block
diagramof the timer/countercircuitry to help you with theseconnections.
NOTE: When installingjumpers on this header,make surethat only onejumper is installedin eachgroup of
threeor four CLK pins.
sl
osc
EC1
EC2
oT0
osc
ECl
EC2
oT1
osc
EC1
EC2
Fig.1-3- UserTimer/Counter
ClockSourceJumpers,
P4
t-4
2 MHz
(XTAL)
8254 PIT
v F 9 10
I/O CONNECTOR
P2
EXTCLKl
EXTCLK2
EXTGATEl
EXTGATE2
OUTO/ OUT1
I
oT0|
osc I
I
E C 1|
I
TRIGGER
our / our2
CircuitBlockDiagram
Fig.1-4- 8254Timer/Counter
P5 -
User Timer/Counter Gate Source (Factory Settings: All Gates: +5V)
This header connector,shown in Figure l-5, lets you selectthe gate sourcesfor the user available 8254 timer/
counters,TC0, TCI, and TC2. The factory settingties all threegateshigh, to an on-board+5 volt source.You can
connect any or all of the gatesto either of two external gate inputs (the first sourcelabeled EGTl on the headerand
EXT GATEI atP2-42, and the secondsource labeledEGT2 on the headerand EXT GATE? atP2-46). Figure 1-4
showsa block diagramof the timer/countercircuitry to help you with theseconnections.
NOTE: When installingjumpers on this header,make surethat only onejumper is installedin eachgroup of
threeGATE pins.
iffi:::,
'll . o
lEGr2
oll o< l+sv
ill . o lEcrl
rll . o
lecre
fttE*ir
GateSourceJumpers,P5
Fig.1-5- UserTimer/Counter
1-5
P6 -
Single-Ended/Differential Analog Inputs (Factory Setting: S (16 Single-Ended))
This headerconnector,shown in Figure l-6, is usedwith switch 52 to configurethe VF9l0 for 8 differential,
8 single-endedwith dedicatedgrounds, or 16 single-endedanaloginput channels.When operatingin the l6 input
single-endedmode, threejumpers must be installedacrossthe S pins. When operatingin the 8 single-endedwith
dedicatedgroundsor 8 differentialmode,threejumpersmust be installedacrossthe D pins. The switch settingson
52 can then be usedto individually configurechannelsfor single-endedor differentialoperation.DO NOT install
jumpers acrossboth S and D pins at the sametime!
P6
s
D
s
H
D
S
D
Fig. 1-6 P7 -
Single-Ended/DifferentialAnalogInput SignalType Jumpers, P6
Analog Input voltage Range and Polarity (Factory Setting: 5v, BI (12.5 volts))
P7, shown in Figure l-7, setsthe analoginput voltagerangeand polarity. The boardcan be set up to operate
over a rangeof5 or l0 volts, unipolaror bipolar.The board'sfour possiblerangesare 0 to +5,0 to +10, +2.5, and
t5 volts. The rangeand polarity are set accordingto your specificationswhen orderingthe board.Figure 1-7 shows
the factory settingof -2.5 to +2.5 volts (if no rangewas specifiedwhen ordering).
NOTE: If you changethe analog input range and/or polarity, you should recalibratethe board according to the
instructions in Chapter 6, Calibration. Otherwise, you may get erroneousdata.
5V
10v
UNI
BI
P7
Fig. 1-7- AnalogInputVoltageRangeand Polarity,p7
P8 - DAC 1 Output VoltageRange(FactorySetting:+5 to -5 volts)
This headerconnector,shownin Figure1-8,setstheoutputvoltagerangefor DAC I at 0 to +5, +5, 0 to +10,or
+10 volts.Two jumpersmustbe installed,
oneto selecttherangeandoneto selectthemultiplier.Thetop two
jumpersselecttherange,bipolar(t5) or unipolar(5).Thebottomtwojumpersselectthemultiplier,X2 or Xl. When
a jumperis on theX2 multiplierpins,therangevaluesbecome
110 and10.Thetableon thenextpageshowsthe
fourpossiblecombinations
ofjumpersettings.
Thisheaderdoesnothaveto be setthesameasp9.
t-6
JumpersOop to Bottom)
Voltage Range
5
f5
x1
x2
-5 to +5 volts
OFF
ON
ON
OFF
0 to +5 volts
ON
OFF
ON
OFF
- 1 0t o + 1 0 v o l t s
OFF
ON
OFF
ON
0 to +10 volts
ON
OFF
OFF
ON
+5
x1
x2
P8
DACl
Fig.1-8- DAC1 OutputVoltageRangeJumper,P8
P9- DAC 2 OutputVoltageRange(FactorySetting:+5to -5 volts)
This headerconnector,shown in Figure 1-9, setsthe output voltagerangefor DAC2 at 0 to +5, *5, 0 to +10, or
+10 volts. Two jumpers must be installed,one to selectthe rangeand one to selectthe multiplier. The top two
jumpers selectthe range,bipolar (+5) or unipolar (5). The bottom two jumpers selectthe multiplier, X2 or X1. When
a jumper is on the X2 multiplier pins, the rangevaluesbecome+10 and 10.The table below showsthe four possible
combinationsof jumper settings.This headerdoesnot have to be setthe sameas P8.
Jumpers(Topto Bottom)
Voltage Range
5
+5
xl
x2
-5 to +5 volts
OFF
ON
ON
OFF
0 to +5 volts
ON
OFF
ON
OFF
- 1 0t o + 1 0 v o l t s
OFF
ON
OFF
ON
0 to +10 volts
ON
OFF
OFF
ON
5
+5
x1
x2
P9
H
D AC2
Fig.1-9- DAC2 OutputVoltageRangeJumper,Pg
t-7
Sl -
Base Address (Factory Setting: 300 hex (768 decimal))
One of the most common causesof failure when you are first trying your boardis addresscontention.Someof
your computer'sVO spaceis alreadyoccupiedby internalVO and other peripherals.When the boardattemptsto use
VO addresslocationsalreadyusedby anotherdevice,contentionresultsand the boarddoesnot work.
To avoid this problem,the VF910 has an easily accessiblefive-positionDIP switch, S l, which lets you select
in the computer'sUO. Shouldthe factory settingof 300 hex (768 decimal)be
any one of l6 startingaddresses
you
your
unsuitablefor
system,
can selecta differentbaseaddresssimply by settingthe switchesto any one of the
valueslisted in Table 1-2. The tableshowsthe switch settingsand their correspondingdecimaland hexadecimal(in
parentheses)
values.Make surethat you verify the order of the switch numberson the switch (l through4) before
settingthem. When the switchesarepulled forward,they are OPEN, or set to logic l, as labeledon the DIP switch
package.When you set the baseaddressfor your board,recordthe value in the table insidethe back cover.Figure
1-10 showsthe DIP switch set for a baseaddressof 300 hex (768 decimal).
Table1-2- BaseAddressSwitchSettings,51
Base Address
Decimal/ (Hex)
Switch Setting
4321
BaseAddress
Decimal/(Hex)
Switch Setting
4321
5r2| (200)
544t (220)
0000
768/ (3oo)
1000
0001
800/ (320)
t00l
s76| (240)
0010
832t (340)
r010
608t (260)
0011
8@ I (360)
t01t
640t (280)
0100
8e6/ (380)
I 100
672| (2AO)
0101
928/ (3A0)
ll0l
7U t (zCO)
0t
960/ (3C0)
1ll0
736 | (2E0)
0111
992| (3E0)
lllr
t0
0 = c l o s e d ,1 = o P e n
Fig.1-10- BaseAddress
Switch,51
l-8
52 -
DifferentiaUSingle-Ended Ground Switch (Factory Setting: OPEN)
DIP switch 52, shown in Figure 1-11,is usedin conjunctionwith headerconnectorP6 to set up the analog
inputs for 8 differential,8 single-endedwith dedicatedgrounds,or l6 single-endedoperation.When the eight
switchesare OPEN (forward),they support8 differentialor l6 single-endedinputs,dependingon the settingof P6.
When the switchesare CLOSED (back),they support8 single-endedinputs with dedicatedgrounds.With P6 set
to D, switchescan be individually set for differentialor single-endedwith groundoperation.Switch I setschannel l,
switch 2 setschannel2, etc.The tablebelow showsthe threeconfigurationsfor P6 and 52.
Settings
InputConfiguration
P6Jumpers
52 Switches
8 DIFF
D
OPEN
8 SE with AGND
D
1 6S E
S
CLOSED
OPEN
Fig.1-11- Differential/Single-Ended
GroundSwitch,52
Pull-up/Pull-down Resistorson Digital VO Lines
The 8255 programmable peripheral interface provides l6 TTUCMOS compatible digital VO lines which can be
interfaced with external devices. Theselines are divided into three groups: eight Port A lines, four Port C Lower
lines, and four Port C Upper lines. (The eight lines ofPort B are usedfor internalboardfunctions.)You can install
and connectpull-up or pull-down resistorsfor any or all of thesethreegroupsof lines. You may want to pull lines
up for connectionto switches.This will pull the line high when the switch is disconnected.Or, you may want to pull
lines down for connection to relays which control turning motors on and off. Thesemotors turn on when the digital
lines controlling them are high. The Port A lines of the 8255 automaticallypower up as inputs,which can float high
during the few moments before the board is first initialized. This can causethe external devices connectedto these
Iines to operateerratically.By pulling theselines down, when the dataacquisitionsystemis first turnedon, the
motors will not switch on beforethe 8255 is initialized.
To use the pull-up/pull-down feature,you must first install resistor packs in any or all of the three locations
between the 8255 and VO connector,labeled PA, PCL, and PCH. PA takes a lO-pin pack, and PCL and PCH take
6-pin packs.
After the resistor packs are installed, you must connectthem into the circuit as pull-ups or pull-downs. Locate
the three-hole pads on the board below the resistor packs.They are labeled G (for ground) on one end and V (for
+5V) on the other end. The middle hole is common. PA is for Port A, PCL is for Port C Lower, and PCH is for Port
C Upper. To operate as pull-ups, solder a jumper wire between the common pin (middle pin of the three) and the V
pin. For pull-downs, soldera jumper wire betweenthe commonpin (middle pin) and the G pin. Figure 1-12 shows
Port A lines with pull-ups, Port C Lower with pull-downs, and Port C Upper with no resistors.
r-9
8255
I
PonrAJ
(PAo-7)
)
(.
Y' o
PULL.DOWN
V
c f
PoRr
L O W E F{
(Pco-3)
[
+5V
YCH
I
€o
Ponrc f
ffi?T
I
to Digitall/O Lines
andPull-downs
Fig. 1-12- AddingPull-ups
Gm, Gain Multiplier Circuitry
The VF910 has softwareprogrammablebinary gainsof 1,2,4, and8. A gain multiplier circuit, Gm, is provided
so that you can easily configure special gain settingsfor a specific application. Note that when you use this feature
and set up the board for a gain of other than l, all of the input channelswill operateonly at your custom gain
settings.In other words, if you install circuitry which gives you a gain multiplier of 10, then the four programmable
gains availableare 10, 20,40, and 80.
Gm is derived by adding resistorsR10 and Rl 1 and trimpot TR3, all located in the upper center areaof the
board.The resistorsand trimpot combineto set the gain, as shownin the diagramand formula in Figure 1-13.
As shown in Figure l-13, a solder short must be removed from the board to activate the Gm circuitry. This short
is locatedon the bottom side of the boardunderUl7 (}.D7lzIC). Figure 1-14showsthe locationof the solder
short.
l-10
Removesoldershort
(seeFigure1-14)
To calculate
Gm:
=
[
(
T
R
3
Gm
+ R 1 1 ) / R 1 O1] +
Fig.1-13- GainCircuitry
andFormula
for Calculating
Gm
RemoveSolderShort
BetweenThese2 Padson
Bottom Side of Board
Fig. 1-14- Diagramfor Removalof SolderShort
l-l I
CHAPTER 2
BOARD INSTALLATION
The VF910 boardis easyto install in your IBM PCD(T/AT or
compatiblecomputer.It can be placedin any slot, shortor fullsize.This chaptertells you step-by-stephow to install and connect
the board.
aa
L-L
Board Installation
Keep the boardin its antistaticbag until you areready to install it in your computer.When removing it from the
bag, hold the boardat the edgesand do not touch the componentsor connectors.
Before installing the boardin your computer,checkthejumper settings.ChapterI reviews the factory settings
and how to changethem. If you needto changeany settings,refer to the appropriateinstructionsin Chapter1. Note
that incompatiblejumper settingscan result in unpredictableboardoperationand erraticresponse.
To install the board:
l. Turn OFF the power to your computer.
2. Removethe top cover of the computerhousing(refer to your owner's manualif you do not alreadyknow
how to do this).
4. Selectany unusedshortor full-size expansionslot and removethe slot bracket.
5. Touch the metal housing of the computer to dischargeany static buildup and then remove the board from its
antistaticbag.
6. Holding the boardby its edges,orient it so that its card edge(bus)connectorlines up with the expansionslot
connectorin the bottom ofthe selectedexpansionslot.
7. After carefully positioningthe board in the expansionslot so that the card edgeconnectoris restingon the
computer'sbus connector,gently and evenlypressdown on the boarduntil it is securedin the slot.
NOTE: Do not force the board into the slot. If the board does not slide into place, remove it and try again.
Wiggling the board or exerting too much pressurecan result in damageto the board or to the computer.
8. After the board is installed, securethe slot bracket back into place and put the cover back on your computer.
The board is now ready to be connectedvia the external VO connector at the rear panel of your computer.
External VO Connections
Figure 2- 1 showsthe VF9 I 0's P2 UO connectorpinout.Refer to this diagramas you make your VO connections.
AlNl+
AINl
AIN1.IAINg/AGND
AlN2+
AIN2
AIN2. IAIN'IO/ AGND
AlN3+
a|l{3
AIN3.IAIN1I/AGND
AlNil+
Alllil
AIN4. IAIN12/AGND
AlN4+
Att{5
A I N s .I A I N 1 3 ' A G N D
AlN6+
AIN6
A I t I s -I A I N l 4 / A G N D
AlNT+
Att{7
A I N T -I A I N l 5 / A G N D
AlNS+
A|l{8
AIN8-IAIN16/AGND
AOUT 1
ANALOG GND
AOUT 2
ANALOG GND
ANALOG GND
ANALOG GND
PA7
PC7
PA6
PC6
PA5
PC5
PA'
PC'l
PA3
PC3
?42
PC2
PA.I
PCI
PAO
PCO
TRIGGER IN
OIGITAL GND
EXT CtXl
EXT GATE1
ouTo/ ouTl
EXTGATE2
TRIGGEB OUT / OUT2
EXT CLX2
+12 VOLTS
+5 VOLIS
-r2 volTs
DIGITAL G'{D
Fig.2-1- P2 VOConnector
PinAssignments
2-3
Connecting the Analog Input Pins
16 Single'Ended, No Dedicated GND. When operatingin the l6 channelsingle-endedmode (P6-S,
S2-OPEN),connectthe high side of the analoginputsto the analoginput channels,AINI throughAINI6, and
connectthe low side to any of the ANALOG GND pins availableat the connector(pins 18,20-22 onP2). Ground
any unusedinputs.Figure 2-2 showshow theseconnectionsare made.
vFg1
0
I / OC O N N E C T O R
P2
I
I
I
lp,"t
a
.
a
MUX
OUT +
SIGNAL
7
souRcE I ls ourl
AIN 15
OUT -
IGN
Fig.2-2- Single-Ended
InputConnections
8 Single'Ended, Dedicated GND. When operatingup to 8 channelsin the single-endedmode with a dedicated
ground for each channel (P6-D, S2-CLOSED), connectthe high side of each analog input to the selectedanalog
input channel, AINI through AIN8, and connect the low side to irs correspondingAGND (AINI- through AINS-).
Ground any unusedinputs. Figure 2-3 shows how theseconnectionsare made. Note that you can mix single-ended
with dedicated ground and differential channelsby setting the individual switcheson 52 to the proper position.
2-4
vF910
I/O CONNECTOR
P2
I
I
I
; PIN 1
aa
.
aa
a
MUX
S I G N A L7
iouRcE I '
z ourJ
(GNo
Fig. 2-3 -
Single-Endedwith Dedicated Grounds Input Connections
8 Differential. When operating in the differential mode (P6-D, S2-OPEN), twisted pair cable is recommended
to reducethe effectsof magneticcoupling at the input. Your signalsourcemay or may not have a separateground
reference.When using the differential mode, you should install a l0 kilohm resistorpack at RN2 on the board to
provide a referenceto ground for signal sourceswithout a separateground reference.
vF910
I/O CONNECTOR
P2
I
I
SIGNAL
r
PIN 1
; o u R c EI '
r our{
i
I
.(PlN2
i
.lil
'lll
'
|
|
AIN 1.
i-\Mr
.
|
I
ii.l
9!Gl!41. 1. I
,huE
AIN l+
-ry.
|
|
OUT r
iptrtg
rtt
ltt
I
7 ourl
(-
lPrN14
MUX
a
ol
1l
A I N7 +
OUT I
I
AIN 7,
GNO
ii
tr
, d" , " I
,r'4ii t i
\-
AIN 8+
L+{^.
AIN 8.
| p r Nz z
Fig.2-4- Differential
lnputConnections
2-5
Connectthe high side of the analoginput to the selecredanaloginput channel,AINI + throughAINS+, and
connectthe low side to the correspondingAIN- pin. Then, for signalsourceswith a separategroundreference,
connectthe ground from the signal sourceto an ANALOG GND (pins l8 and20-22on p3). Figure 2-4 showshow
theseconnectionsare made.Note that you can mix single-endedwith dedicatedground and difierential channelsby
settingthe individual switcheson 52 to the properposition.
Connecting the Trigger In and Trigger Out Pins, Cascading Boards
The VF9l0 boardhas an externaltrigger input (P2-39)and output (P2-43)so that two or more boardscan be
cascadedand run synchronouslyin a "master/slave"configuration.By cascadingtwo (or more) boardsas shown in
Figure 2-5, they can be triggeredto startan A./D conversionat the sametime. Note that when using the external
trigger output (P2-43)suchas on the masterboardin Figure 2-5, you must serthe bottomjumper on p3 to TRIG.
If you apply an externaltrigger to the board'strigger in pin, note that the trigger can be negative-or positivegoing. The pulse durationshould be at least 100 nanoseconds.
When using the TRIGGER OUT, the pulsi must
always be positive-going.
vFg10
I/O CONNECTOF
B O A R DT 1
(MASTER)
SIGNAL /,
souRcEI *
r our{
I
B O A F D* 2
(sLAvE)
MUX
SIGNAL ,
sounce[ *
2 our{
I
P2-1
AlNl +
i
lpz-z
t0K
I
I
AIN1
I
I pz-sg
TRIGGEF IN
Fig.2-5- Cascading
TwoBoardsfor Simultaneous
Sampling
Connecting the Analog Outputs
For eachof the two D/A outputs,connectthe high side of the devicereceivingthe output ro the AOUT channel
(P2-17 or P2-19) and connectthe low side of the deviceto an ANALOG GND (p2-18 orp2-20).
Connecting the Timer/Counters and Digital UO
For all ofthese connections,the high side ofan externalsignalsourceor destinationdeviceis connectedto the
appropriate signal pin on the VO connector,and the low side is connectedto any DIGITAL GND.
Runningthe 910DIAGDiagnosticsProgram
Now that your board is ready to use,you will want to try it out. An easy-to-use,
menu-drivendiagnostics
program,910DIAG, is includedwith your examplesoftwareto help you verify your board's operation.You can also
use this program to make surethat your curent baseaddresssettingdoesnot contendwith anotherdevice.
2-6
CHAPTER 3
HARDWARE DESCRIPTION
This chapterdescribesthe featuresof the VF9l0 hardware.The
major circuits are the A,/D which consistsof the V/F converter and
associatedtiming and counting,the D/A, and the digital VO lines.
Three timer/countersfrom the user 8254 areavailable at the VO
connectorfor your use.Board intemrptsare also describedin this
chapter.
3-l
The VF9l0 boardhas threemajor circuits,the AID which consistsof the VIF converterand associatedtiming
and counting,the D/A, and the digital VO lines.Threetimer/countersfrom the user8254 is availableat the UO
connectorfor your use.Figure 3- I showsthe block diagramof the board.This chapterdescribeshardwarewhich
makesup the major circuits.It also discussesinterrupts.
16 ANALOG INPUTS
0-1 0V, asv, 0-5V. r2.5V
8 0tFF./16S.E./
8 S.E, WITH AGND
Fig.3-1 - VF910BlockDiagram
A/D ConversionCircuitry
The VF910 board performs analog-to-digital conversionsusing a voltage-to-frequencyconverter and timing and
counting circuits. This circuitry functions as an exceptionally accurateintegrating converter. The V/F converter
convertsthe input voltageto a frequencybetween0 and systemclock + 2 (full scale),and this frequencyis counted
by the frequency counter for a specified period of time. The following paragraphsdescribethe A,/D circuitry.
Analog Inputs
The input type can be set for 8 differential, 8 single-endedwith dedicatedground, or l6 single-endedby
opening and closing switches on DIP switch 52 and setting the jumpers on P6. You can mix differential and singleended with dedicatedground as describedin Chapter 1 under the 52 settingsdiscussion.Single-endedoperationis
typically used when the analog input voltage sourceis close to the board and the voltage levels are fairly trigh
(greater than 10.5 volts). The differential mode provides noise immunity when long cable runs are unavoidable,
signal levels are low, or surrounding electrical noise is high. Software programmablebinary gains of l, 2, 4, and g
let you amplify low level signalsto more closely matchthe board'sinput ranges.Thesegainscan be customizedfor
even greaterinput control by addinga gain multiplying resistorcircuit as describedin Chapter l.
J-J
The input rangeis jumper-selectable
for 5 volts or 10 volts, unipolaror bipolar.The availablerangesare 0 to
+5, 0 to +10, -2.5 to +2.5, and -5 to +5 volts. The boardis factory serfor -2.5 to +2.5 volts. Shouldyou needto
changethe input rangeand/orpolarity, you shouldrecalibratethe boardaccordingto the instructionsin Chapter6,
Calibration. Each channelhas an input impedanceof greaterthan l0 megohms.Overvoltageprotectionof t35 Vdc
is provided at the multiplexer.
V/F Converter
The V/F converterreceivesan input voltageand convertsit to a correspondingfrequencywhich is then read
from the frequencycounteras 20-bit data.The conversiontime varies,dependingon the degreeof accuracyyou
want in your result and the speedof the systemclock. The softwareselectablesystemclock can be set for 0.5, l, or
2 MHz A 1 MHz clock providesthe bestspeedversuslinearity tradeofffor most applications.At 0.5 MHz, linearity
improves,but the conversiontime doubles.A2MHz clock performsthe fastestconversions,but sacrificeslinearity.
With a systemclock of I MHz, a l2-bitconversion is performedin about 8 milliseconds,a 16-bit conversionin 131
milliseconds,and an l8-bit conversionin 524 milliseconds.
The V/F converterusedon the VF9l0 is Analog Devices' AD652 monolithic synchronousV/F converter.This
extremelylinear deviceis clockedby the programmablesystemclock. The systemclock signalis divided by 2 on
the chip, resultingin the 0 to systemclock -+2 frequencyrangeof the converter.The samesystemclock is usedto
gatethe timer circuitry, which meansthat you will get accurateconversionseven if the clock frequencyshoulddrift.
To compensatefor gain drift in the V/F converter,a trimpot is provided on the board. Chapter 6, Calibration,
tells you how to adjustthis trimpot.
Timing and Counting Circuits
The timing and countingcircuits usedwith the VIF converterare shown in Figure 3-2. Yery simply, the 8254
opensa window of time and the 20-bit countercountsthe frequencyoutput of the V/F converter.
8254 PtT
Fig.3-2-VlF TimingandCounting
BlockDiagram
3-4
The 20-bit counterhas two flags: counteroverflow and measurementoverflow. The counteroverflow flag is set
overflow flag is set if two or
if the 20-bit counteroverflows within a singlemeasurement
cycle. The measurement
more measurementcycleshave beenexecutedwithout the counterbeing clearedbetweencycles.
As shown in Figure 3-2, the 8254 programmableintervaltimer (PIT) containsthree 16-bit timers.Two of these
timers are cascadedto form a32-bit timer which gatesthe frequencycounters.The frequencycountersare opened
for a window of time specifiedby this 32-bit timer. You programthe timer for the amountof time that you want the
frequencycountersto count, accordingto your desiredresolution.The remainingtimer in the 8254 (timer 2) is the
samplecounter.The 8254 data sheetis includedin Appendix C to assistyou in using this timer.
A 20-bit counteris usedto count the frequencyoutput of the V/F converterfor the period specifiedby the 8254
timer. For singleconversions,a conversionis started,the 20-bit counteris gatedfor a specifiedperiod of time, and
the value is read.For continuousconversions,the first conversionis started,the 20-bit counteris gatedfor a specified period of time, and, when the conversionis ready,the programmableservicecounterstartsits countdown
during which the converteddata is readand the input channeland gain for the next conversionare set.When the
servicecounterreaches0, the next conversionis triggered.
D/A Converter
Two independentl2-bit analogoutputchannelsare includedon the VF910. The analogoutputsare generated
jumper-selectable
by two 12-bit D/A converterswith independent
output rangesof +5, +10, 0 to +5, and 0 to +10
volts. The +10 volt rangehasa resolutionof 4.88 millivolts, the t5 and 0 to +10 volt rangeshavea resolutionof
2.44 millivolts, and the 0 to +5 volt rangehasa resolutionof |.22 millivolts. The D/A outputscan be updated
simultaneouslyor asynchronously.
Timer/Counters
Three I 6-bit, 8 MHz timer/counterson the user8254,TC0, TC 1, and TC2, supporta wide rangeof timing and
counting functions.Each timer/counterhastwo inputs,CLK and GATE, and one output,OUT. Figure 3-3 showsthe
timer/countercircuitry and the connectionsyou can make to the inputsand outputs.Each timer/countercan be
programmed as binary or BCD down countersby writing the appropriatedata to the command word, as describedin
Chapter4. The commandword also lets you set up the mode of operation.The six programmablemodesare:
Mode 0
Mode I
Mode 2
Mode 3
Mode 4
Mode 5
Event Counter (Intemrpt on Terminal Count)
Hardware-Retriggerable
One-Shot
Rate Generator
SquareWave Mode
Software-TriggeredStrobe
Hardware Triggered Strobe (Retriggerable)
These modes are detailed in the 8254 Data Sheet,reprinted from Intel in Appendix C.
Digital VO, Programmable Peripheral Interface
The 8255 programmableperipheralinterface(PPI) is usedfor rtigital VO functions.This high-performance
TTL/CMOS compatible chip has 24 digital UO lines divided into two groups of 12 lines each:
Group A Group B -
Port A (8 lines) and Port C Upper (4 lines);
Port B (8 lines) and Port C Lower (4 lines).
Port A and Port C are available at the external VO connector.P2. Port B is dedicatedto on-board functions and
is not availablefor your use.You can usethe 16 lines ofPorts A and C in one ofthese threePPI operatingmodes:
Mode 0 - Basic input/output. Lets you use simple input and output operation for a port. Data is written to or
read from the specified port.
Mode 1 - Strobed input/output. Lets you transfer VO data from Port A in conjunction with strobesor handshakingsignals.
3-5
vF9t0
VO CONNECTOR
P2
2 MHz
(XTAL)
8254 PtT
EXTCLKl
EXTCLK2
EXTGATEl
EXTGATE2
EGr2
i
OUTO/ OUT1
+5V
EGT2I
L---
ll
TRIGGER
ouT / ouT2
EXTERNAL
-l
our
Fig.3-3- User8254fimer/Counter
Circuitry
Mode 2 - Strobed bidirectional inpuUoutput.Lets you communicatebidirectionally with an external device
through Port A. Handshakingis similar to Mode l.
These modes are detailed in the 8255 Data Sheet,reprinted from Intel in Appendix C.
Interrupts
The VF910 has two software selectableintemrpt sources:end-of-convert and external trigger. The end-ofconvert (EOC) line can be used to interrupt the computer when a conversion is completed.When the 32-bit timer's
count reaches0, the counter gate closes,the conversion is complete, and the EOC line goes high. When in the
continuous convert mode, the service time begins, and you can read the data, changethe channel/gain settings,and
reset the 20-bit counter. The EOC line can be connectedthrough software, as shown in the VO Map discussionin
Chapter 4. On power-up, the EOC line is disabled.Changethe IRQ channel if necessaryfor your application. If you
connect the end-of-convert to one of the interrupt channels,an intemrpt will occur when the line transitions from
low (converting) to high (not converting). The external trigger line (trigger in, P2-39) can be used to feed in an
external interrupt signal or loop a signal back onto the board, such as the output oftimer/counter 2,to be used as an
interrupt. When using the external trigger line as an external interrupt signal, the polarity (intemrpt on rising or
falling edge) is set at BA + 21, bit l. We recommendthat you have an understandingof how to use interrupts in your
system before you connect the end-of-convert to an IRQ channel.
3-6
CHAPTER 4
BOARD OPERATION AND PROGRAMMING
This chaptertells you how to initialize the board and read the
converteddata.It describesoperatingmodes and provides flow
diagramsand a completedescriptionof the VO map to aid you in
programming your VF910 board. The exampleprogramsincluded
on the disk in your board packageare listed at the end of this
chapter.Theseprograms,written in BASIC, Turbo Pascal,and
Turbo C, include sourcecodeto simplify your applicationsprogramming.
Chapter5, Calculating Frequencies,Voltages,and Bits, contains tables,formulas, and examplesto help you understandthe
principlesof V/F conversion.
4-l
Defining the VO Map
The VO map for the VF9l0 is shownin Table 4-l below. As shown,the boardoccupies23 consecutiveVO port
locations.The baseaddress(designatedas BA) can be selectedusing DIP switch S I as describedin Chapter l,
Board Settings.This switch can be accessedwithout removing the board from the computer. S I is factory set at 300
hex (768 decimal).The following sectionsdescribethe registercontentsof eachaddressusedin the VO map.
Table4-1- VF910l/OMap
RegisterDescription
WriteFunction
Read Function
Address t
Decimal/ (Hex)
A/D Data Low Bvte
Read bottomI bits of 20-bit
converteddata word
Reserved
BA+0/(00)
A/D DataMiddleBvte
Readmiddle8 bitsof 20-bit
converteddata word
Reserved
BA+1/(01)
Readtop 4 bitsof 20-bit
A/D Data Hiqh Bvte/Status converteddataword& status Reserved
BA+2/(02)
Readboard readycode
Clearthe 20-bitconversion
counter
BA+3/(03)
8254Timer/Counter
0
Readcountvalue
Loadcountregister
BA+4/(04)
8254Timer/Counler1
Readcountvalue
Loadcountregister
BA+5/(05)
8254Timer/Counter
2
Readcountvalue
Loadcountreqisler
BA+6/(06)
8254 ControlRegister
Reserved
Prooram8254mode
BA+7/(07)
BoardReady/Clear
20-bit
ConversionCounter
Read8-bitPortA digitalinput Program8-bitPortA digital
outputlines
8255 PPI PortA Digitall/O lines
BA+8/(08)
8255 PPI Port B
(A/DChannel/Gain
settings
Select) Readchannel/gain
BA+e/(09)
Programchannel& gain
Read8-bitPortC digitalinput Program8-bitPortC digital
outputlines
8255 PPI PortC Digitall/O lines
BA+10/(0A)
Program8255configuration
BA+11/(0B)
Reserved
Programbottom8 bits of
12-bitDAC 1 data
BA+12l(0C)
DAC 1 HighByte
Beserved
Programtop 4 bitsof 12-bit
DAC 1 data
BA+13/(0D)
DAC 2 Low Byte
Reserved
Programbottom8 bits of
12-bitDAC2 data
BA+1al(0E)
DAC2 HighByte
Reserved
Programtop 4 bitsof 12-bit
DAC 2 data
BA+15/(0F)
0 Readcountvalue
8254 UserTimer/Counter
Loadcountregister
BA+16/(10)
1 Readcountvalue
8254 UserTimer/Counter
Loadcountregister
BA+17l(11)
2 Readcountvalue
8254UserTimer/Counter
Loadcountregister
BA+18/(12)
Reserved
Program8254mode
BA+19/(13)
BoardSetup
Reserved
Programsystemclock,
conversionmodeand
interruptchannel
BA+20/(14)
A/D TriggerMode
Reserved
Programtriggermodeand
parameters
BA+21l(15)
DACS
Resevuodate
Resetsboard
Simultaneously
updateDAC
1 and DAC2
BA+22l(16)
8255 PPI ControlRegister Reserved
DAC 1 Low Bvte
8254 ControlRegister
' BA = BaseAddress
4-3
BA + 0: A/D Data Low Byte (Read Only)
A readprovidesthe low byte (bits 0 through7) ofthe 20-bit converteddatain the conversioncounter.
Bil7
Bit6
Bit5
Bit4
Bit3
Bit2
Bitl
Bit0
D7
D6
D5
D4
D3
D2
D1
DO
BA + 1: ND Data Middle Byte (ReadOnly)
A readprovidesthemiddlebyte(bits8 throughl5) of the20-bitconverted
datain theconversion
counter.
Bit15 Bit14 Bit13 Bit12 Bir11 Bit10 Bit9
BitS
D7
DO
D6
D5
D4
D3
D2
D1
BA + 2: AID Data High Byte (Read Only)
A readprovidesthe high byte (bits l6 through 19) ofthe 20-bit converteddatain the conversioncounter,plus
the counter overflow, measurementoverflow, and conversionready flag status.The counter overflow tells you if the
20-bit conversion counter overflows during a measurementcycle. The measurementoverflow flag tells you if two or
more measurementcycles are executedwithout clearing the counter betweenexecutions.The conversion ready flag
tells you the conversionstatus(conversionrunning or conversionfinished).
Bit19
Bit18
Bit17
Bit16
A,/DConversionStatus
running
0 = conversion
complete
1 = conversion
MeasurementOverflow
CounterOverflow
0 = no overflow
1 = 2 or moremeasurements1 = overflow
withoutcounterreset
0 = ff€sSUlglllents OK
BA + 3: Board Ready/Clear 20-bit Conversion Counter (Read/Write)
A read must give you the value of 82 (52 hex) to indicate that the BA is set properly. A write clears the 20-bit
conversion counter and flags. The data written is irrelevant.
BA + 4: 8254 Timer/Counter 0 (Read/Write)
Two reads show the count in the timer/counter, and two writes load the counter/timer with a new l6-bit value,
LSB followed by MSB. The timer/counter must be loaded in two 8-bit steps.Counting begins as soon as the MSB is
loaded.
This timer/counter, cascadedwith timer/counter I to form a32-bit timer, generatesthe board's internal pacer
clock which controls measurementsand starts and stopsconversions.
4-4
BA + 5: 8254 Timer/Counter 1 (Read/Write)
Two readsshow the count in the timer/counter,and two writes load the counter/timerwith a new l6-bit value,
LSB followed by MSB. The timer/countermust be loadedin two 8-bit steps.Countingbeginsas soon as the MSB is
loaded.
This timer/counter, cascadedwith timer/counter 0 to form a32-bit timer, generatesthe board's internal pacer
clock which controlsmeasurements
and startsand stopsconversions.
BA + 6: 8254 Timer/Counter 2 (Read/Write)
Two readsshow the count in the timer/counter,and two writes load the counter/timerwith a new l6-bit value,
LSB followed by MSB. The timer/countermust be loadedin two 8-bit steps.Countingbeginsas soonas the MSB is
loaded.
This timer/counter,with its clock input connectedto the output of timer/counterl, can be usedas a sample
counter to provide a hardwarecount of the number of samplesbeing taken.
BA + 7: 8254 Control Word (Write Only)
Accessesthe 8254 PIT control register to directlv control the three timer/counters.
D7
D6
D5
D4
D3
02
D1
DO
BCD/Binary
0 = binary
1=BCD
CounterSelect
Selecl
00 = Counter
r0
01 = Counter1
10= Counter
2
11= readbacksetting
BA + 8: PPI Port A -
Read/Load
00 = latchingoperation
0'l = read/load
LSBonly
10= read/load
MSBonly
11= read/load
LSB.thenMSB
CounterModeSelect
000= Mode0. eventcount
001= Mode1, programmable
1-shot
010= Mode2, rategenerator
0'l 1 = fvls6s3, squarewaverategenerator
100= Mode4, software-triggered
strobe
101= Mode5, hardware-lriggered
strobe
Digital VO (Read/Write)
Transfers the 8-bit Port A digital input and digital output data between the board and an external device. A read
transfers data from the external device, through P2, and into PPI Port A; a write transfersthe written data from
Port A through P2 to an external device.
BA + 9: PPI Port B -
ChanneUGain Select (Read/Write)
A write programs the analog input channel and gain for the next conversion.This port must be set up as a
Mode 0 output for proper operation.
Reading this register shows you the current bit settings.
4-5
Analog Input
Channel Select
0000 = channel 1
0001= channel2
0010= channel3
001'l = channel4
0100 = channel5
0 1 0 1= c h a n n e6l
0110 = channel7
0 1 1 1= c h a n n e8l
ChannelGain
00=x1
0 1= Y 2
10=x4
11=x8
BA + 10: PPI Port C -
1000= channel9
1 0 0 1= c h a n n e 1
l0
1 l1
1010=channe
1 0 1 1= c h a n n e 1
l 2
1100=channe
1 l3
1 1 0 1= c h a n n e 1
l4
111 0 = c h a n n e 1
l 5
1 1 1 1= c h a n n e1l 6
Digital UO (Read/Write)
Transfers the two 4-bit Port C digital input and digital output data groups (Port C Upper and Port C Lower)
between the board and an external device. A read transfersdata from the external device, through P2, and into PPI
Port C; a write transfers the written data from Port C through P2 to an external device.
BA + 11: 8255 PPI Control Word (Write Only)
When bit 7 of this word is set to l, a write programs the PPI configuration. The PPI must be programmed so
that Port B is a Mode 0 output port, as shown below (X = don't care).
D6
D7
Mode Set
1 = active
D5
D4
D3
D1
DO
-l
rrasti
|
|
1",
rde Seler>t
= mode
= mode
r c= mode
i3:
I
I
I
I
I
D2
Port A
0 = output
1 = input
Port C Upper
0 = output
1 = input
GroupA
4-6
|
|
Port
t C Lower
o = output
c
1 = iinput
r
|
|
I
Port B
I
= output
0
|
1 = input
I
I
ModeSelect
0=mode0
''1
1= m o d e
mode1
|
L_
_-i3t"l
|
The table below shows the control words for the 16 possible Mode 0 Port VO combinations.The control words
which set Port B as an input cannotbe usedon the VF910.
8255Port UOFlow Directionand ControlWords.Mode0
GroupA
GroupB
ControlWord
Port A
Port C
Upper
Port B
PortC
Lower
Binary
Decimal
Hex
Outpul
Output
Output
Output
10000000
128
80
Output
Outpul
Output
Input
10000001
129
81
Output
Output
Input
Output
10000010
130
82
Output
Output
lnput
Input
10000011
131
83
Output
Input
Output
Outpul
10001000
136
88
Output
Input
Output
Input
10001001
137
89
Output
Input
Input
Output
10001010
138
8A
Output
Input
Input
Input
10001011
139
8B
Input
Output
Output
Output
10010000
1M
90
Input
Output
Output
Input
10010001
145
91
Input
Outpul
Input
Output
10010010
146
92
Input
Outpul
Inpul
Input
10010011
147
93
Input
Inpul
Output
Outpul
10011000
152
98
Input
lnput
Outpul
Input
10011001
153
99
Input
Input
Input
Outpul
10011010
1g
9A
Input
Input
Input
Input
10011011
155
9B
When bit 7 of the PPI control word is set to 0, a write can be used to individually program the Port C lines.
D7
D6
D5
D4
D3
SeUResel
FunctionBir
0 = active
D2
Bit Select
ggg = pCO
001 = PC1
010 = PC2
0 1 1= P C 3
100 = PC4
1 0 1= P C S
1 1 0= P C 6
1 1 1= P C 7
4-7
D1
DO
Bit SeuReset
sel
0=setbitto0
1=s€tbittol
For example,if you want to setPort C bit 0 to l, you would set up the control word so that bit 7 is 0; bits 1, 2,
and 3 are 0 (this selectsPCO);and bit 0 is t (this setsPCOto l). The control word is set up like this:
SetsPGOto 1:
(writtento BA + 'l1)
07
D6
D5
D4
D3
D2
D1
X = don't care
SeUResel
FunctionBir
DO
Set PCO
Bit Select
ggg= pCO
BA + 12: D/A Converter l LSB (Read/Write)
A writeprograms
theDACI LSB (eightbits).
BA + 13: D/A Converter l MSB (Read/Write)
A write programstheDACI MSB (four bits) into D0 throughD3; D4 throughD7 areirrelevant.
BA + 14: D/A Converter2 LSB (Read/Write)
A write programstheDAC2 LSB (eightbits).
BA + 15: D/A Converter2 MSB (Read/Write)
A write programstheDAC2 MSB (four bits) into D0 throughD3; D4 throughD7 areirrelevant.
DACLSB
DAC MSB
D7
D6
D5
D4
D3
D2
D1
DO
Bit7
Bit 6
Bil5
Bit4
Bit3
Birz
Bir 1
Bit0
D7
D6
D5
D4
D3
D2
D1
DO
B i r1 1
Bir10
Bit9
Bit8
X
BA + 16: User 8254 Timer/Counter 0 (Read/Write)
Two reads show the count in the timer/counter,and two writes load the counter/timer with a new l6-bit value,
LSB followed by MSB. The timer/countermust be loadedin two S-bit steps.Countingbeginsas soonas the MSB is
loaded.
BA + 17: User 8254 Timer/Counter I (Read/Write)
Two reads show the count in the timer/counter, and two writes load the counter/timer with a new l6-bit value,
LSB followed by MSB. The timer/countermust be loadedin two 8-bit steps.Countingbeginsas soon as the MSB is
loaded.
BA + 18: User 8254 Timer/Counter 2 (ReadlWrite)
Two reads show the count in the timer/counter, and two writes load the counter/timer with a new 16-bit value,
LSB followed by MSB. The timer/countermust be loadedin two 8-bit steps.Counting beginsas soon as the MSB is
loaded.
4-8
BA + 19: User 8254Control Word (Write Only)
Accessesthe 8254PIT controlregisterto directlycontrolthethreeusertimer/counters.
BCD/Binary
0 = binary
1=BCD
CounterSelect
00 = Counter0
01 = Counter1
10= Counter
2
11= readbacksetting
Read/Load
00 = latchingoperation
01 = read/loadLSB only
10 = read/loadMSB only
11 = read/loadLSB, then MSB
CounterModeSelect
gQQ= Mode0, eventcount
1-shot
QQI= Mode1, programmable
010= Mode2, rategenerator
011= Mode3, squarewaverategenerator
strobe
100= Mode4, software-triggered
strobe
101= Mode5, hardware-triggered
BA + 20: Board Setup Register (Write Only)
A write sets the PC's interrupt channel,the A,/D conversionmode, the system clock speed,and the service timer
divider. Bits 0 through2 areusedto selectthe interruptchannel.Threesettings,000, 100,and l0l, disablethe
interrupt. If an tRQ channel is programmed,the interrupt selectedat BA + 2l is automatically enabledon that
channel.
The service time is programmableto provide you with as much time as you need to read the data, clear the
counter,and changethe channeland gain.
ServiceTimerDivider
00 = .5 psec
01 = 62.5psec
10= 126.5lrsec
11= 254.5psec
ConversionMode
0 = single
1 = continuous
SystemClock
00=2MHz
01=1MHz
10= 0.5MHz
11= externalclock
4-9
lnterruptChannelSelect
000= interruptdisabled
001= lRQ5
010= lRQ6
011= IRQT
100= interrupt
disabled
disabled
101= interrupt
1 1 0= t R Q 2
1 1 1- r R Q 3
BA + 21: A/D Trigger Mode Register (Write Onty)
This registersetsup varioustriggeringparametersfor conversions.Bit 0 setsthe trigger mode, internalor
external.In the externaltrigger mode,a conversioncan be startedon the rising or falling edgeof the trigger,
dependingon the settingofbit 1. Bit 3 setsthe intenupt source.Bit 4 can be usedto starta conversionin internal
trigger mode.In the singleconversionmode,only one measurement
is taken.In the continuousmode, after the start,
the boardis continuouslyconverting.
SoftwareTrigger
1 = startconvert
(internal
trigger)
TriggerSelect
0 = externaltrigger
1 = internaltrigger
ExternalTriggerPolarity
0 = startconverton risingedge
1 = startconverton fallingedge
IRQSelect
0=EOC
1 = External
Trigger
BA + 22: Reset/UpdateDACs (Read/Write)
A readresetsthe board.Thedatawrittenis irrelevant.
A write simultaneously
updatesthetwo D/A outputswith thelatcheddata.If thedatawrittento eitherchannel
hasnot beenupdatedsincethelastconversion,
theoutputofthe corresponding
DAC will notchange.
4-10
A/D Conversions
Before you can starttaking A,/D conversions,you must clear the 20-bit counterand programthe 8254 timer.
The software provided with your board contains example programs for board initialization.
You can monitor the conversionstatususing the end-of-convertbit at VO addresslocationBA + 2. When bit 7
of this word is low, a conversionis in progress.When it goeshigh, the conversionis completed.Note that the endof-convertline can also be monitoredthrougha softwareprogrammableIRQ line if it is enabled.
Programming the 8254 Timer
Two of the 8254's 16-bit timers are cascadedto form a32-bit timer which gatesthe 20-bit conversioncounter.
The timer is clocked by the same system clock which suppliesthe V/F converter.Timer 0 and timer 1 are programmed with the values that will open the conversion gate for the desiredtime window. In the example programs
included with your board,timer 0 is alwaysset at 32. This divides the input frequencyof systemclock by 32, which
produces an output frequency of system clock -+32 going into timer l. For a system clock of I MHz, this is:
To set for 32,
LSB = 32 (20),
MSB = 0 (00)
Then, timer 1 is programmed with the correct divider value to take readings at the desiredresolution. For
example,if you want a resolutionof 16 bits with the systemclock programmedto run at I MHz, then you must
program timer I to further divide the output of timer 0 by 4095. This producesan output frequency of 7.629 Hz,
which will open the 20-bit conversioncountergatefor 131.072millisecondsgiving you a 16-bit resolution:
To setfor 4095,
LSB= 255(FF),
MSB= 15(0F)
To setfor 32,
LSB= 32 (20),
MSB= g 1gg;
NOTE: The above example is for both single and continuousconversions.Note that you must always subtract
1 from the value you load into timer I in order to have an accuratecount. This is done to compensatefor how the
8254 handles single countdown operationsfor cascadedtimers. In the continuous mode, the sampling rate is
determined by:
fs = I - (gatetime + servicetime).
As you can see,the timing calculationscan be somewhatcomplex. The formulas for calculating the counts to
load into the timers are given in Chapter 5. Chapter 5 also provides tables and formulas for decimal counts. These
are helpful for voltage-basedresolutions, such as a resolution of 100 microvolts. Here, you can refer to the following
table to help you determine the count to be loaded into the timers for bit-basedresolutions.
4-tl
Resolution
Timer0 MSB Timer 1 LSB
Timer0 LSB
Timer 1 MSB
(DecimaUHex) (DecimaUHex)(DecimaUHex) (DecimaUHex)
12bits
32t20
0/00
255 | FF
0/00
13 bits
32t20
0/00
255| FF
11 0 1
14 bits
32t20
0/00
255/ FF
3/03
15bits
32/20
0/00
255/ FF
7 t07
16bits
32t20
0/00
255| FF
15/0F
17bits
32t20
0/00
255 I FF
3 1/ 1 F
18 bits
32120
0/00
255 I FF
63/3F
This chapter'sfinal examplefor the 8254timer is a portionof an initializationprogram,writtenin BASIC,
which showsyou how to setup the 8254timers0 and I sothattheyopentheconversioncounterfor a time periodof
givingyou a l6-bit resolution
131.072milliseconds,
with a I MHz systemclock.Thetimer I divideris 4095.In this
example,TWC standsfor the 8254controlregisterwhichis addressed
at BA + 7 (decimal),TA standsfor timer 0
which is addressed
at BA + 5. All valuesarein hex.
at BA + 4. andTB standsfor timer I whichis addressed
OUT TWC, &H34
ouT Twc, &H74
u u r . ' 1A ,
OUT TA,
OUT TB,
OUT TB,
& . n zu
&HO
&HFF
&HF
'SET
'SET
'SET
'SET
,SET
.SET
U P T I M E R O A S M O D E2
U P T I M E R T A S M O D E2
TIMER O DTVIDERLSB
TIMER O DIVIDER MSB
TIMER 1 DIVIDER LSB
TIMER 1 DIVIDER MSB
(LSB
(MSB
(LSB
(MSB
32 FOR DIVIDER OF 32)
O FOR DIVIDER OF O)
255 FOR DIVIDER OF 255)
15 FOR DIVIDER OF ].5)
Initializing the 8255 PPI
The eight Port B lines of the 8255 PPI control the channel and gain selection.Port B is programmed at VO
addresslocationBA + 9:
D7
D6
D5
D4
D3
D2
D1
DO
Analoglnput
ChannelSelect
0000= channel1 1000= channel9
0001= channel2 1001= channel10
00 = channel
0010
3 1010=channelll
12
0011=channel4 1011= channel
0100= channel
5 1100= channel13
0101= channel
6 1 1 0 1= c h a n n e1l4
0110= channel
7 1 1 1 0= c h a n n e1l5
0 1 1 1= c h a n n e l S1 1 1 1= c h a n n e1 l6
ChannelGain
QQ=x1
01=;l
10=x4
11=xB
4-12
To use Port B for thesefunctions, the 8255 must be initialized so that Port B is set up as a Mode 0 output port.
This is done by writing this datato the PPI control word at VO addressBA + 11 (X = don't care):
D6
D7
D5
D4
D3
D2
D1
DO
Clearing the Board
It is good practice to start your program by resetting the board. You can do this by performing a read ofthe
RESET port at BA + 22.
Setting the Channel
To select a conversion channel, you must assignthe appropriatevalues to bits 0 through 3 at BA + 9. The table
below shows you how to determine the bit settings.Note that in the single convert mode, if you don't want to
change the gain setting when programming a new channel setting, you must preservethe gain portion of the channel-gaindata when you set the channel.
x
cH3 cH2 cHl
x
cH1
0
0
cH0
Channel
cH3
cHz
0
I
1
T
10
1
0
0
1
0
11
1
1
1
1
x
Channel
cH3
cH2
1
0
0
0
0
4
0
0
0
0
5
0
I
0
0
b
t
0
.l
7
0
0
12
13
't4
1
1
0
15
I
0
1
1
2
3
cH0 B A + 9
x
I
16
cH1
0
0
cH0
0
0
1
0
1
1
0
{
1
1
0
0
1
'l
1
0
1
t
1
0
1
1
1
1
Setting the Gain
To selectthe gain (1,2,4, or 8), you must assignthe appropriatevaluesto bits 4 and 5 at BA + 9. The table
below shows you how to determine the bit settings.Note that in the single convert mode, if you don't want to
change the channel setting when programming a new gain setting, you must preservethe channel portion of the
channel-gain data when you set the gain.
x
G1
x
x
GO
x
x
Gain
G1
GO
1
0
2
0
0
4
1
0
I
1
1
4-r3
1
x
BA+9
Conversion Modes
The A/D circuitry can perform conversionsin two modes,Single Convert and Continuous Convert. The board is
typically used in the Continuous Convert mode.
. Single Convert Mode
The Single Conveft mode lets you perform a single A,/D conversioneach time you write a 1 to the Software
Trigger (Start Convert) bit, bit 4 at BA + 2l . BA + 20, bit 3 shouldbe set to 0 for singleconversions.Figure 4- I
showsthe timing diagramfor this mode,and Figure4-2 providesa flow diagram.
StartConversion
End-of-Convert
Counters
Enabled
Counters
Enabled
131.072
ms
A,/DCountersGate
Counting
ReadCount
Counting
Fig.4-l - SingleConvertModeTimingDiagram
4-14
Read Count
Setsystemclock,single
conversion
mode,internaltrigger
Program8254Timerfor desired
gatetime
Clear Conversion
SelectChannel
& Gain
ChangeChannel?
Start Conversion
End-of-Convert
Readcontentsof counters
Fig.4-2- SingleConvertModeFlowDiagram
. Continuous Convert Mode
The ContinuousConvertmode lets you perform continuousconversionsby writing a 1 to the SoftwareTrigger
(StartConvert) bit, bit 4 at BA + 2l . BA + 20, bit 3 shouldbe setto 1 for continuousconversions.Fisure 4-3 shows
the timing diagramfor this mode,and Figure 4-4 providesa flow diagram.
StartConversion
End-of-Conve-
l#
A,/DCountersGate
-$(-service Timed
:st.ozzms
Counting
ReadCount
Counting
Interrupt
(if enabled)
Fig.4-3- Continuous
ConvedModeTimingDiagram
4-16
ReadCount
Setsystemclock,servicetime,
continuous
convertmode.
internaltrigger
Program8254Timerfor desired
gatetime
ClearConversion
SelectChannel& Gain
StartConversion
End-of-Convert
Readcontentsof counters
Clear Conversion
StopProgram
Fig.4-4- Continuous
ConvertModeFlowDiagram
. Cascading Boards
Two or more boardscan be cascadedand triggeredso that conversionsare performedsimultaneouslyon each
board.Figure 4-5 providesa flow diagramfor cascadedoperation.Chapter2 showshow to connectthe boardsfor
simultaneoustriggering.
Boards 1&2
Set systemclock,
singleconversionmode,
Board1: internaltrigger
Board2: externaltrigger,rising
edge
Boards1&2
Program8254Timerfor desired
gatetime
Boards1&2
ClearConversion
Boards'l&2
SelectChannel& Gain
StartConversion
End-of-Convert
Boards1&2
Readcontentsof counters
Boards1&2
StopProgram
Fig.4-5- CascadedBoards,SingleConvedModeFlowDiagram
Reading the Converted Data
After a conversionis completed,the datais readfrom the 20-bit conversioncounter.The excerptbelow from an
exampleBASIC program showsyou how datais readfrom the counter.The datais read in threebytes,the low,
middle, and high byte, at threeVO addresslocations,BA + 0, BA + l, and BA + 2. The upperhalf of the byte
You must mask this bit out beforeusing the value.
containsthe statusbit of the measurement.
' R E A D C O U N T E RL O W B Y T E
ADLB = INP(BA)
' R E A D C O U N T E RM I D D L E B Y T E
ADMB = INP(BA + 1)
A D H B = I N P ( B A + 2 ) A N D O H E ' R E A D C O L T N T EHRI G H B Y T E
R E S U L T = ( ( A D L B + ( A D M Bx 2 5 6 ) + ( A D H B x 5 5 5 3 6 ) ) x C F
The last line of this example program shows you how to convert the result into the true frequency output by the
V/F converter. After performing the multiplication by the bit weight for each of the four bytes read, you must then
multiply the result by a correction factor, CF, in order to find the true frequency of the signal you measured.The
correction factor is the inverse of the amount of time you had the counter gated open for counting
(CF=1+GateTime).
For example,if you count a l0 Hz signalfor I second,your count would be 10.This is multiplied by a correction factor of l, which is I + I second.If you count the same l0 Hz signalfor 0.5 seconds,your count would be 5'
This is multiplied by a correctionfactor of 2 (l - 0.5 seconds)which againgives you the true frequencyof 10 Hz.
Counting 10 Hz for 2 secondsgives you a count of 20 which is then multiplied by a colrection factor of 0.5 ( 1 +-2
seconds)for a result of l0 Hz. In contrast,a more complexexampleis counting for l3l.O72 milliseconds(a l6-bit
resolution).The correctionfactoris I +.131072,or7.629.
D/A Conversions
The two D/A converterscan be individually programmedto convert l2-bit digital words into a voltagein the
rangeof t5, +10, 0 to +5, or 0 to +10 volts. DAC1 is programmedby writing the 12-bit digital data word to BA + 8
and BA + 9. DAC2 is identical,with the dataword written to BA + 10 and BA + I l. The DACs are updatedby
writing ro BA + 22.The following tableslist the key digital codesand correspondingoutput voltagesfor the D/A
converters.
D/AConverterUnipolarCalibrationTable
ldeal Output Voltage(in millivolts)
D/A Bit Weight
0to+5V
0to+10V
4095 (Max.Output)
4998.8
9997.6
2048
2500.0
5000.0
1024
1250.0
2500.0
1250.0
512
625.00
256
312.50
625.00
128
156.250
312.50
64
78.125
1s6.250
32
39.063
78.125
16
19.5313
39.063
8
9.7656
19.5313
4
4.8828
9.7656
2
2.4414
4.8828
1
1.2207
2.4414
0
0.0000
0.0000
4-19
D/AConverterBipolarCalibrationTable
ldeal Output Voltage (in millivolts)
D/A Bit Weight
4095(Max.Output)
!5V
r10v
+4997.6
+9995.1
2048
0.0
0.0
1024
-2500.0
-5000.0
512
-3750.0
-7500.0
256
-4375.0
-8750.0
128
-4687.5
-9375.0
64
-4843.8
-9687.5
32
-4921.9
-9843.8
16
-4960.9
-9921.9
8
-4980.5
-9960.9
4
-4990.2
-9980.5
2
-4995.1
-9990.2
1
-4997.6
-9995.1
0
-5000.0
-10000.0
User-Available8254Timer/Counter
An 8254 programmable interval timer provides three l6-bit, 8 MHz timer/countersfor timing and counting
functions such as frequency measurement,event counting, and interrupts. All three timer/countersare available for
your use.Figure 4-6 showsthe timer/countercircuitry.
Each timer/counter has two inputs, CLK in and GATE in, and one output, timer/counter OUT. They can be
programmed as binary or BCD down countersby writing the appropriatedata to the command word, as describedin
the VO map section at the beginning of this chapter.
One of three clock sources,the on-board 2MHz crystal, external clock I (EXT CLKI, P2-41), or external clock
2 (EXT CLK2,P2-45) can be selectedas the clock input. The diagram shows how theseclock sourcesare connected
to the timer/counters.
Three gate sourcesare available: +5V on-board (always tied high), external gate I (EXT GATEI, P2-42), or
external gate 2 (EXT GATE2, P2-46). The diagram shows how thesegate sourcesare connectedto the timer/
counters.
The output from timer/counter 0 or I is jumper-selectable.The selectedoutput is available at the OUTO/OUTI
pin (P2-44). Timer/counter 2's output is available at the TRIGGER OUT/OUT2 (P2-43) if it is enabled by placing
thejumper on P3 acrossthe appropriatepins. The diagram shows how theseoutputs are connected.
The timer/counters can be programmedto operatein one of six modes, dependingon your application. The
following paragraphsbriefly describeeach mode.
Mode O Event Counter (Interrupt on Terminal Count). This mode is typically used for event counting.
While the timer/counter counts down, the output is low, and when the count is complete, it goes high. The output
stays high until a new Mode 0 control word is written to the timer/counter.
4-20
vF910
r/o coNNEcTon
P2
EXTCLXl
EXTCLK2
EXTGATEl
EXTGATE2
EGr2
|
OUTO/ OUT1
TIMER/
COUilTEN
2
CLX
6ATE
OUT
Fig.4-6- UserE254Timerl0ounter
Circuitry
Mode 1, Hardware-Retriggerable One-Shot. The output is initially high and goes low on the clock pulse
following a trigger to begin the one-shotpulse. The output remainslow until the count reaches0, and then goes high
and remains high until the clock pulse after the next trigger.
Mode 2, Rate Generator. This mode functions like a divide-by-N counter and is typically used to generatea
real-time clock intemrpt. The output is initially high, and when the count decrementsto l, the output goes low for
one clock pulse. The output then goes high again, the timer/counter reloadsthe initial count, and the processis
repeated.This sequencecontinues indefi nitely.
Mode 3, Square Wave Mode. Similar to Mode 2 exceptfor the duty cycle output, this mode is typically used
for baud rate generation.The output is initially high, and when the count decrementsto one-half its initial count, the
output goes low for the remainder of the count. The timer/counterreloads and the output goes high again. This
processrepeatsindefi nitely.
Mode 4, Software-Triggered Strobe. The output is initially high. When the initial count expires, the output
goes low for one clock pulse and then goes high again. Counting is "triggered" by writing the initial count.
Mode 5, Hardware Triggered Strobe (Retriggerable). The output is initially high. Counting is triggered by
the rising edge of the gate input. When the initial count has expired, the output goeslow for one clock pulse and
then goes high again.
Digital VO
The 16 8255 PPl-baseddigital VO lines can be used to transfer data betweenthe computer and external devices.
The digital input lines can have pull-up or pull-down resistorsinstalled, as describedin Chapter 1.
Interrupts
The VF910 has two software selectableintemrpt sources:End-of-convert and external trigger. The selected
intemrpt can be monitored through a software-selectableintemrpt channel,IRQ2 through IRQ7. The EOC line is
low whenever an A,/D conversion is in progress.When the signal transitions to a high (logic l) state,an interrupt is
sent to the computer telling it that the conversion is completed.The external trigger line generatesan intemrpt on the
rising edge or falling edge of the signal fed into P2-39, dependingon the setting of bit I at BA + 2 I .
4-21
ExamplePrograms
Included with the VF9l0 is a setof exampleprogramsthat demonstratethe useof many of the board's features.
Theseexamplesare in written in C, Pascal,and BASIC. Also includedis an easy-to-usemenu-drivendiagnostics
program,9lODIAG, which is especiallyhelpful when you are first checkingout your boardafter installationand
when calibrating the board (Chapter 6).
Before using the softwareincludedwith your board,make a backupcopy of the disk. You may make as many
backupsas you need.
C and Pascal Programs
These programs are sourcecode files so that you can easily develop your own custom software for your VFgl0
board.In the C directory,VF9I0.H and VF9lO.INC containall of the functionsneededto implementthe main C
programs. H defines the addressesand INC contains the routines called by the main programs. In the Pascaldirectory, VF91O.INCcontainsall of the proceduresneededto implementthe main Pascalprograms.
Analog-to-Digital:
READ
EXTTRIG
INTRPT,MULTI
Demonstratesbasic operation of A/D.
Similar to READ except that an external trigger is used.
Single and multiple channelA/D conversionswith intem.rpt
Digital UO:
DIGITAL
Simple program the shows how to read and write the digital VO lines.
Digital-to-Analog:
DAC
Showshow to usethe DAC. UsesA./D channel1 to monitor the output of the DAC.
Interrupts:
INTRPT
Showsthe bareessentialsrequiredfor using interrupts.
BASIC Programs
Theseprogramsaresourcecodefiles so thatyou canyou caneasilydevelopyour own customsoftwarefor your
VF9l0 board.
Analog-to-Digital:
READ
EXTTRIG
Demonstratesbasic operation of A/D.
Similar to READ except that an external trigger is used.
Digital VO:
DIGITAL
Simple program the shows how to read and write the digital VO lines.
Digital-to-Analog:
DAC
Showshow to usetheDAC. UsesA/D channelI to monitorthe outputof DAC.
4-22
CHAPTER 5
CALCULATING FREQUENCIES,VOLTAGES,AND BITS
This chaptercontainstables,formulas,and examplesto help
you understandthe principlesof V/F conversion.Includedare
exampleswhich show how to calculatethe timer (binary and
decimal)to gatethe frequencycountersand how to calculatethe
correctionfactor,tablesshowingthe expectedoutput frequencies
for selectedinput voltagesfor eachinput range,and formulas for
converting frequencyto voltage and bits.
5-1
5-2
This chaptershowsyou how to calculatethe contentsof the 8254 timer which gatesthe 20-bit AfD conversion
resolution),how to calculatethe true
counterin both binary @it-basedresolution)and decimal(voltage-based
frequency ofa conversion using the correction factor, expectedfrequency outputs for selectedinput voltages for
each of the four analog input ranges,and how to convert frequency to voltage and bit values.
Calculating the Settingsfor the 8254Timer
When performing voltage-to-frequencyconversions,the resolution of your result is dependenton how long you
look at the output of the converter. On the VF910, a software selectablesystem clock drives the VIF converter. The
converter divides this clock by 2 internally. Therefore, the output from the V/F converter will always be between 0
and the systemclock + 2 (full scale).Using the 20-bit conversioncounter,you look at the output of the V/F converter for a specified period of time and count the number of transitions which occur in the output during that time
frame. You can set your time period for binary or decimal, dependingon whether you want to measureyour
resolutionas a function of bits or voltage.
How long do you want to look at the current conversionbefore starting a new one? The window of time is set
by two l6-bit timers on the 8254 PIT. These timers are cascadedto form a32-bit timer which is programmed to
open up the conversion counter so that you can obtain data at the accuracylevel you need for your application.
Binary Calculations
To determine the binary value to be loaded into the timer for bit-basedresolutions,you must first calculate what
change in the output frequency of the V/F converter you must detect in order to achieve your desiredresolution.
Note that the input voltage range is not a factor in birbased calculations. Then, you must divide the system clock
which drives the 8254 (the sameclock which drives the V/F converter) down to the value of this changein frequency.The result is the value you load into the timer. For example,let's set up the timer for l6-bit conversions.
Calculatethe amountof changeyou must discernfor'16 bits:
216= 65,536,which meansyou must detecta 1 part changein 65,536to have a resolutionof 16 bits.
Next, convertthis resultinto lrequency(0.5 MHz = full scalewith a 1 MHz systemclock):
500,000Hz + 65,536= 7.629394Hz
This meansthat we must detecta changeof 7.629394Hz out of 0.5 MHz. Also notethat this frequency,
7.629394 Hz, is the correctionfactor (see discussionin ConversionPesu/ts and CorrectionFactorsection).
Next, we must dividethe systemclock which drivesthe 8254by the changewe must detectto determinethe value
we must programinto the timer:
1,000,000+ 7.62394= 1,000,000+ (500,000+ 65,536)= 2 x 65,536= 131,072
We need to dividethe systemclock by 131,072to open the timer for the rightamountof time, 131.072milliseconds,
to take 16-bitreadings.
Counter 0 is programmed with the 16 least significant bits of the 32-bit timer word. All of our example programs use binary division and set counter O to 32. When counter 0 is 32, the I MHz clock is divided by 32 for a
resulting31,250 Hz clock into timer l, as shownbelow:
To setfor 32.
LSB= 32 129;,
MSB= 0 (00)
5-3
Then, timer l, which containsthe 16 most significantbits of the 32-bit timer word, is programmed.The value to
be programmed is determinedby:
( 1 3 ' 1 , 0 7 2 * 3 2 ) -1 = 4 0 9 5
The value we must programin timer I is 4095, as shownin the diagrambelow.
To setfor 4095,
LSB= 255(FF),
MSB= 15(0F)
To setlor 32.
LSB= 32 (20),
MSB= 0 (00)
The values calculated using the formulas alreadypresentedwill open the window of the counters for the right
amount of time whenever you are doing conversions.Note that you always subtract 1 from the timer value in order
to correct for the 8254's method of loading and counting. The table below shows the count which must be loaded
into the timers for the listed bit-basedresolutions for Single Convert and for Continuous Convert modes.
Resolution
Timer0 LSB
Timer0 MSB Timer1 LSB
Timer1 MSB
(DecimaUHex) (DecimaUHex)(DecimaUHex) (DecimaUHex)
12 bits
32/20
0/00
255 I FF
0/00
13bits
32t20
0/00
255I FF
1l01
14bits
32120
0/00
255/ FF
3/03
15 bits
32t20
0/00
255/ FF
7 107
16bits
32120
0/00
255 | FF
15/0F
17 bits
32t20
0/00
255 | FF
31/1F
18 bits
32t20
0/00
255| FF
63/3F
5-4
Decimal Calculations
resolutions,you must first calcuTo determinethe decimalvalue to be loadedinto the timer for voltage-based
you
to achieve your desired
must
in
order
V/F
detect
converter
late what change in the output frequency of the
in this calculation.Then,
voltage
range
you
the
input
must
include
resolution.Unlike with the bit-basedformulas,
the
V/F converter) down to
(the
which
drives
clock
same
you must divide the system clock which drives the 8254
For
example,
let's set up the
you
into
the
timer,
result
is
the
value
load
the value of this changein frequency. The
timer for conversionswith a resolutionof 100 microvolts.
Calculatethe amountof changeyou must discernfor 100 microvoltresolutionand an input range of 10 volts:
5 V + 100 pV = 50,000,which meansyou must detecta 1 part changein 50,000to have a resolutionof
100 microvolts.
'l
Next, conveftthis resultinto frequency(0.5 MHz = full scalefor a MHz systemclock):
500,000Hz + 50,000= 10 Hz
This meansthat we must detecta changeof 10 Hz out of 0.5 MHz. Also note that this frequency,10 Hz, is the
correction factor (see discussion in Conversion Resultsand CorrectionFacforsection).
Next,we must dividethe systemclockwhich drivesthe 8254by the changewe must detectto determinethe value
we must programinto the timer:
1 , 0 0 0 , 0 0 0 +1 0 = 1 0 0 , 0 0 0
We need to dividethe 1 MHz clock by 100,000to open the timerfor the rightamountof time, 100 milliseconds,to
take 100 microvoltresolutionreadings.
Counter 0 is programmed with the 16least significant bits of the 32-bit timer word. When counter 0 is 2000, the
I MHz clock is divided by 2000 for a resulting0.5 kHz clock into timer 1.
Then, timer 1, which contains the 16 most significant bits of the 32-bit timer word, is programmed.The value to
be programmed is determined by:
(100,000+2000)-1=49
The value we must program in timer I is 49, as shown in the diagram below.
To setfor 49,
LSB= 49 (31),
MSB= 0 (00)
To setfor 2000,
LSB= 208(D0),
MSB= 7 (07)
Like in binary calculations, the values calculatedusing the formulas already presentedwill open the window of
the counters for the right amount of time wheneveryou are doing conversions.Note that you always subtract I from
the timer value in order to correct for the 8254's method of loading and counting. The two tables on the following
page show the count which must be loaded into the timers for input rangesof 5 volts or l0 volts for the listed
voltage-basedresolutions.
5-5
For s-volt Input Ranges:
Resolution
Timer0 LSB
Timer1 MSB
Timer0 MSB Timer1 LSB
(Decimal/Hex) (Decimal/Hex) (Decimal/Hex) (DecimaUHex)
1 0m V
250| FA
0/00
3/03
0/00
1mV
208/ D0
7/07
4 t04
0/00
1 0 0p V
208/ D0
7t07
49/31
0/00
1 0p V
208 | DO
7107
243| F3
1/01
For 10-voltInput Ranges:
Resolution
Timer 1 MSB
Timer0 LSB
Timer0 MSB Timer1 LSB
(DecimaUHex) (DecimaUHex)(DecimaUHex) (DecimaUHex)
10mV
'l
mV
244 | F4
1/01
3/03
0/00
208/ D0
7 107
9/09
0/00
100trV
208| D0
7 /07
99/63
0/00
1 0p V
208/ D0
7 /07
231t E7
3/03
ConversionResultsand CorrectionFactor
For eachconversion,when you count the output ofthe V/F converter,you incrementa 20-bit counterby one for
eachpulsecounted.For example,let's programthe timer to open the gatefor the counterfor a period of 131.072
milliseconds.We read the datafrom the counterin three8-bit words,ADLB (low byte), ADMB (middle byte), and
by the count,you calculate:
ADHB (high byte). To find the true frequencyrepresented
True Frequency= [(ADLB+ (ADMBx 256) + (ADHBx 65536)]x CF
where CF is the correctionfactor.
After performing the multiplication by the bit weight for eachof the three bytes read, you must then multiply
the result by CF, the correction factor, in order to find the true frequency of the signal you measured.The correction
factor is the inverse of the amount of time you had the counter gated open for counting:
CF = 1/GateTime
For example,if you count a l0 Hz signalfor I second,your count would be 10.This is multiplied by a correction factor of l, which is the sameas I -r I second.If you count the same l0 Hz signalfor 0.5 seconds,your count
would be 5. This is multiplied by a conection factor of 2 ( I + 0.5 seconds)which again gives you the true frequency
of 10 Hz. Counting l0 Hz for 2 secondsgives you a count of 20 which is then multiplied by a correctionfactor of
0.5 (l : 2 seconds)for a result of l0 Hz. In contrast,a more complexexampleis counting for 131.072milliseconds
(our l6-bit resolutionexamplegiven above).The correctionfactor is I : 0.131072,or 7 .629.
The upper four bits of the high byte (ADHB) contain the measurementoverflow, counter overflow, and
conversion done flags. These flags must be maskedout when you calculatethe frequency or voltage value.
5-7
Input Voltagesand Output Frequencies
The analoginputs can be set up for four ranges:0 to +5, 0 to +10, -2.5 to +2.5, and -5 to +5 volts. The following
tablesshow the expectedoutput frequenciesfor selectedinput voltagesin eachrangefor a I MHz systemclock.
For 0 to +5Vrange:
(Frequency= 100,000x InputVoltage)
InputVoltage
OutputFrequency
5V
500.000Hz
3.75V
375,000Hz
2.5V
250,000Hz
1.25V
Hz
125.000
OV
0Hz
For 0 to +10Vrange:
(Frequency= 50,000x InputVoltage)
InputVoltage
OutputFrequency
10v
500.000Hz
7.5V
Hz
375.000
5V
Hz
250.000
2.5V
Hz
125.000
OV
0Hz
For -2.5to +2.5Vrange:
(Frequency= 100,000x (lnputVoltage+ 2.5))
InputVoltage
OutputFrequency
+2.5Y
500.000Hz
+1.25V
Hz
375.000
OV
250,000Hz
-1.25V
125,Q00Hz
-2.5V
0Hz
For -5 to +5V range:
(Frequency = 50,000x (lnput Voltage + 5))
InputVoltage
OutputFrequency
+5V
500.000Hz
+2.5V
375.000Hz
OV
250.000Hz
-2,5V
Hz
125.000
-5V
0Hz
5-8
Input Voltage Calculations
The general formula for calculating the input voltage when the frequency and voltage range are known is:
Input Voltage = (Frequency(system clock + ZNoltage Range) - Otfset
The offset is 0 for unipolar voltage rangesand one-half the range for bipolar voltage ranges.
For 0 to +5 volts:
-0
lnput Voltage= (Frequency/100,000)
For 0 to +10 volts:
-0
lnput Voltage= (Frequency/50,000)
For -2.5 to +2.5 volts:
InputVoltage= (Frequency/l00,000)- 2.5
For -5 to +5 volts:
-5
InputVoltage= (Frequency/50,000)
Bit Calculations
The general formula for calculating the bit value when the frequency and resolution are known is:
Bit Value - (Frequency/(system
clock* 2/2N))- Offset
where N = the numberof bits of the desiredresolution.
and the offset is 0 for unipolaroperationand 0.5 x 2Nfor bipolaroperation.
For example,to calculatethe bit value for a l2-bit resolution:
Unipolar:
BitValue= (Frequency/(system
clock+ 2/4096))- 0
= Frequency/122.O7
Bipolar:
- 2048
Bit Value = (Frequency/(system
clock* 214096))
- 2048
= (Frequency/122.07)
For example,to calculate
thebit valuefor a l6-bit resolution:
Unipolar:
Bit Value = (Frequency/(system
clock+ 2/65,536))- 0
= FrequencyZ.629
Bipolar:
Bit Value = (Frequency/(system
clock+ 2/65,536))- 32,768
= (Frequencyfi.629) - 32,768
5-9
CHAPTER 6
CALIBRATION
This chaptertells you how to calibratethe VF910 using the
9lODIAG diagnosticsprogramincludedin the examplesoftware
packageand the four trimpots on the board. Thesetrimpots calibrate the VIF convertergain and offset and the D/A circuitry.
Calibration is necessarywheneveryou changethe analog input
voltage range and/or polarity.
6-l
This chaptertells you how to calibratethe V/F convertergain and offset and the D/A converterX2 multiplier.
The offset and full-scaleperformanceof the board'sV/F converteris factory-calibratedfor operationat the input
voltagerangeyou specifiedwhen orderingthe board.If you changethe rangeand/orpolarity, you must recalibrate
your board.Any time you suspectinaccuratereadings,you can checkthe accuracyofyour conversionsusing the
procedurebelow, and make adjustmentsas necessary.
Calibrationis done with the boardinstalledin your PC. You can accessthe trimpots with the computer'scover
removed.Power up the computerand let the boardcircuitry stabilizefor 15 minuiesbeforeyou startcalibrating.
RequiredEquipment
The following equipmentis requiredfor calibration:
.
.
.
.
9IODIAG DiagnosticsProgram(includedwith examplesoftware)
PrecisionVoltage Source:+10 volts
Digital Voltmeter: 5-l/2 digits
Small Screwdriver(for trimpot adjustment)
Figure 6-1 showsthe boardlayout.The four trimpotsusedfor calibration,TRl, TR2, TR4, and TR5, are located
in the uppercenterareaofthe board.
V/F Calibration
Two adjustmentsare made to calibrate the V/F converter. One is the offset adjustment,and the other is the full
scale,or gain, adjustment.Trimpot TR2 is usedto make the offset adjustment,and trimpot TR1 is usedfor gain
adjustment.
s,| BASEADDRESS
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4
Fig.6-1- BoardLayout
6-3
Connectyour voltagesourceto channelI on the VF910 board.Use Table 6-l to set the voltagefor your input
rangeand desiredadjustment(offset or gain). Then run the 9lODIAG program,adjustingthe appropriatetrimpot
until the input voltage and V/F converter output reading match.
Table 6-1 - A/D Offset and Gain Adjustments
InputVoltage
T R 1 .G a i n
TR2.Oflset
0 to +5 volt input range:
.0001v
.0001v
+4.75V
+4.75 V
0 to +10volt input range:
.0001v
.0001v
+9.75V
+9.75V
-2.5to +2.5volt input range:
OV
OV
+2.25Y
+2.25Y
-5 to +5 volt input range:
OV
+4.75Y
OV
+4.75Y
D/A Calibration
The D/A converter requires no calibration for the Xl ranges(0 to +5 and 15 volts). The following paragraph
describesthe calibration procedure for the X2 multiplier ranges.
To calibrateforX2 (0 to +10 or+10 volts), set the DAC output voltagerangeto 0 to +10 volts (umpers on X2
and 5 on P6, AOUTl, or P7, AOUT2). Then, program the correspondingD/A converter (DACI or DAC2) with the
digital value 2048. The ideal DAC output for 2048 at X2 (0 to +10 volt range) is 5.0000 volts. Adjust TR4 for
AOUT1 and TR5 for AOUT2 until 5.0000 volts is read at the output. Table 6-2 lists the ideal output voltages per bit
weight for unipolar ranges and Table 6-3 lists the ideal output voltagesfor bipolar ranges.
6-4
Tabfe6-2- D/A ConverterUnipolarCalibrationTable
ldealOutputVoltage(in millivolts)
D/ABit Weight
0to+5V
0to+10V
4095(Max.Output)
4998.8
9997.6
2048
2500.0
5000.0
1024
1250.0
2500.0
512
625.00
1250.0
256
312.50
625.00
128
156.250
312.50
64
78.125
156.250
32
39.063
78.125
16
19.5313
39.063
8
9.7656
19.5313
4
4.8828
9.7656
2
2.4414
4.8828
1
1.2207
2.4414
0
0.0000
0.0000
Table6-3- D/A ConverterBipolarGalibrationTable
ldealOutputVoltage(in millivolts)
D/A Bit Weight
15v
4095(Max.Output)
+4997.6
+9995.1
2048
0.0
0.0
1024
-2500.0
-5000.0
512
-3750.0
-7500.0
256
-4375.0
-8750.0
128
-4687.5
-9375.0
64
-4843.8
-9687.5
32
-4921.9
-9843.8
t6
-4960.9
-9921.9
8
-4980.5
-9960.9
4
-4990.2
-9980.5
2
-4995.1
-9990.2
1
-4997.6
-9995.1
0
-5000.0
-10000.0
6-5
!10v
APPENDIX A
VF91OSPECIFICATIONS
VF910 Characteristics typical@25'c
lnterface
IBMPCrff/AT compatible
Switch-selectable
baseaddress,l/O mapped
interrupt
Software-selectable
Analog lnput
ground,16single-ended
S single-ended
withdedicated
I differential,
.............>10
megohms
........
Inputimpedance,
eachchannel
to +5,0 to +10,X2.5,or +5 volts
fnputranges
....................0
protection
..+35Vdc
Overvoltage
1,2,4 & 8 plusGmgainmultiplier
selectable
Gains,software
max
typ;Q.25o/o,
..................0.05%,
Gainerror
...+10volts,max
Commonmodeinputvoltage
.10psec,max
Settling
time(gain= 1)......
.....4D652
. . . . . . . .S. .y n c h r o n o u s
.......to18 bits(19 pV, S-voltrange)
.................0.005o/o,
rltax
.......Seetablebelow
Type.............
Besolution
Linearityerror............
Conversionspeed...........
..............cMos
82c55
......................16
Number
of lines
............TTUCMOS
Logiccompatibility
.............
(Configurable
resistors)
withoptionall/OpulFup/pull-down
min
....................4.2V,
High-level
output
vo|tage...................
..................0.45V,
max
voltage
..................
Low-level
output
.2.2V,min;5.5V,max
inputvoltage
High-level
.-0.3V,min;0.8V,max
inputvoltage
Low-level
pA
............+10
Inputloadcurrent
Inputcapacitance,
. . . . . . . . . . . . . . . . .p. .F. . 1 0
C ( | N ) @ F = 1 M. H
. . .z. . . . . . . . .
Outputcapacitance,
pF
......20
C(OUT)<@F=1MHz
..........AD7237
D/A Converter
.........2channels
Analogoutputs
...12bits
Resolution
.....0to +5, +5, or 0 to +10 volts
Outputranges
to +5, +5, and 0 to +9.2 volts
Guaranteedlinearityacrossoutputranges....................0
..................+1
LSB,max
Relativeaccuracy......
+5 LSB, max
Full-scaleaccuracy
...........+1
LSB,max
Non-linearity
10 psec,max
Settlingtime .............
.........cMos
82cs4
Timer/Counters...........
1 independent)
Three16-bitdowncounters(2 cascaded,
modes
operating
6 programmable
inputsource
...........
External
clock(8 MHz,max)or
Counter
on-board
2 MHzclock
................Avai1ab1e
externally
outputs
Counter
gateor alwaysenabled
........External
Countergatesource..
Miscellaneous lnputs/Outputs (PC bus-sourced)
+5 volts,+12volts,ground
Current Requirements
520mA @+5 volts
A-3
Gonnector
50-pin rightangle shroudedbox header
Environmental
temperature
Operating
..................0
to+70'C
...................-40
to +85"C
Storagetemperature
Humidity
Size
Short slot - 3.875"Hx 5.30"W{99mmx 135mm)
VF910A"/DConversionResolution
(1 MHzSystemClock)
RESOLUTION
10 bits
11bits
12 bits
13 bits
14 bits
15 bits
'16
bits
17 bits
18 bits
CONVERSIONTIME
2.048msec
4.096msec
8.192msec
16.384msec
32.768msec
65.536msec
131.072
msec
262.144msec
524.288msec
A-4
FREQUENCY
488.28H2
244.14Hz
122.O7Hz
6 1 . 0 4H z
30.52Hz
1 5 . 2 6H z
7.63H2
3.81 Hz
1 . 9 0H z
APPENDIX B
P2 CONNECTORPIN ASSIGNMENTS
P2 Connector:
DIFF.
S.E.
AlNl +
AINl
AINI- IAINg / AGNO
AlN2+
AIN2
A t N 2 . I A t N l O/ A G N D
AlN3+
AIN3
A I N 3 -I A I N 1 1/ A G N D
AlN4+
AIN4
AIN4- IAIN12/AGND
AlN4+
AIN5
AIN5- IAIN13 / AGNO
AlN6+
AIN6
AIN6. IAIN14/AGNO
AlNT+
AINT
A I N 7 .I A I N l 5 / A G N D
AlNS+
AINS
AIN8. IAINl6/AGND
AOUT 1
ANALOG GND
AOUT 2
ANALOG GND
ANALOG GND
ANALOG GND
PA7
PC7
PA6
PC6
PA5
PC5
PA4
PC4
PA3
PC3
?42
PC2
PA.I
PCI
PAO
PC0
TFIGGER IN
EXT CLKl
TFIGGER OUT / OUTz
EXT CLK2
PIN49
P I N 50
DIGITAL GNO
EXT GATE1
ouTo/ ouTl
EXT GATE2
+12 VOLTS
+5 VOLTS
-t2 voLTs
D I G I T A LG N D
MatingConnectorPart Numbers
Manufacturer
PartNumber
AMP
1-746094-0
3M
3425-7650
B-3
B-4
APPENDIX C
COMPONENT DATA SHEETS
c-l
IntervalTimer
Intef82C54Programmable
DataSheetRePrint
intel'
82C54
TIMER
INTERVAL
CHMOSPROGRAMMABLE
I Compatlblewlth all Intel and moet
other mlcroprocessors
r Hlgh Speed,"Zero Walt State"
Operatlonwlth 8 MHz8086/88and
80186/188
I HandlesInputs from DC to 8 MHz
- 10 MHzfor 82C54-2
I AvallableIn EXPRESS
- StandardTemperatureRange
- ExtendedTemperatureRange
t ThreeIndependent16-bltcounters
I Low Power CHMOS
- lcc : 10 mA @8 MHzCount
frequency
r CompletelyTTL Compatlble
r Slx ProgrammableCounterModes
r Blnaryor BCDcountlng
I Status Read Back Command
I AvallableIn 24-PlnDIP and 28-PlnPLCC
whichis
standard
The lntel82C54is a high-performance,
8254counter/timer
CHMOSvarsionof the industry
systsmdesign.lt providesthree
designedto solvethe timingcontrolproblemscommonin microcomputer
independent
16-bitcounters,
eachcapableof handlingclockinputsup to 10 MHz.All modesare software
programmable.
The 82C5/is pincompatible
withthe HMOS8254,and is a supersetof the 8253.
Six programmable
timer modesallowthe 82C54to be used as an €ventcount€r,elapsedtime indicator,
programmable
one-shot,and in manyotherapplications.
The 82C54is fabricatedon lntel'sadvancedCHMOSlll technologywhichprovideslow powerconsumption
withperformance
equalto or gr€aterthanthe equivalentHMOSproduct.The82C54is availablein 24-pinDIP
and 28-pinplasticleadedchipcanier(PLCC)packages.
|rlocx
conr'cR
321,,n,6
Oa
5
Dt
6
Or
,
Or
I
9
t0
f,!
PT
il
ratSsttl
Ao
Ar
231241-3
PI.ASTICLEADEDCHIPCARRIER
aa
xt
Ycc
Or
Ot
t2
Fo
c-3
Dt
D.
Dr
5
a
Or
Ot
o0
.cll0
our 0
ortE 0
ox0
231211-1
Flgure1.82C54BlockDlagram
ar
t0
m
Ar
il
,
&
tl
I
It
clt 2
ou? 2
t
ra
t0
$
tt
la
l2
t3
2
clt r
oltE r
OUt t
23124-2
Dagramsarelof pinr€lerenc€only.
Packagesiz€sare not to scel€.
Flgure2.82C54Pinout
3-83
S.ptcmbGr1e89
Ordcr llumbon 2312aalos
intef
82C54
Table1.PlnDescrlption
Symbol
Dz'Do
PlnNumber
DIP
PLCC
1-8
2-9
CLK O
9
OUTO
10
GATEO
GND
11
12
OUT1
13
GATE1
CLK 1
14
GATE2
OUT2
CLK2
15
16
't7
10
12
13
Type
tlo
Clock0: Clockinputof Counter
0.
Output0: Outputof Counter0.
I
Gate0: Gateinputof Counter0.
Ground:Powersupplyconnection.
14
16
17
18
19
o
20
o
1.
Out1:Outputof Counter
Gate 1: Gateinputof Counter1
Clock1: Clockinputof Counter1.
21
23-22
c-s
21
24
I
RD-
22
26
I
WF'
23
27
Vee
24
NC
tri-statedata bus lines.
Data:Bidirectional
connectedto systemdata bus.
o
18
20-1I
At, Ao
Function
Gate2: Gateinputof Counter
2.
Out2: Outpulof Counter
2.
Clock2: Clockinputof Counter
2.
Address:Usedto selectoneof thethreeCounters
or the ControlWordRegisterfor reador write
operations.
Normallyconnectedto thesystem
addressbus.
Ar
Ao
Selects
0
0
Counter0
1
0
Gounter1
1
0
Gounter2
1
1
ControlWord
Reqister
ChipSelectA lowon thisinputenablesthe82C54
to respondto FiDandWFIsignals.RDandWFiare
ignoredotherwise.
Read Control:This input is low duringGPUread
operations.
WriteControl:Thisinputis lowduringGPUwrite
operations.
Power:+ 5Vpowersupplyconnection.
No Connect
28
1 , 1 1 ,1 5 , 2 5
sired delay. After the desired delay, the 82C5a witl
interruptthe CPU.Softwareoverheadis minimaland
variablelength delays can easily be accommodated.
FUNCTIONALDESCRIPTION
General
The 82C54is a programmableintervaltimer/counter
designed for use with Intel microcomputersystems.
It is a generalpurpose,multi-timingelementthat can
be treated as an aray ol llO ports in the system
software.
The 82C54 solves one of the most common problems in any microcomputersystem,the generation
of accuratetime delays under softwarecontrol. Instead of setting up timing loops in software,the programmerconfiguresthe 82C54to matchhis requirements and programsone of the countersfor the deg-8/,
Some of the other counter/timer functions common
to microcomputerswhich can be implementedwith
the 82C54 are:
.
o
o
.
.
o
.
o
Real time clock
Even counter
Digitalone-shot
Programmablerate generator
Sguare wave generator
Binaryrate multiplier
Complexwavelorm generator
fumplex motor controller
irttef
82C54
Block Dlagram
CONTROLWORDREGISTER
The ControlWordRegister(seeFigure4)is selected
by the Read/WriteLogicwhen Ar, Ao : 11. lf the
CPU then does a write operationto the 82C54,the
data is stored in the ControlWord Registerand is
interpretedas a Control Word used to define the
operationof the Counters.
DATABUSBUFFER
This3-state,bi-directional,
8-bitbutferis usedto interfacethe 82C54to the systembus(seeFigure3).
1:+;"{
I
The ControlWord Registercan only be written to;
status informationis availablewith the Read-Back
Command.
clr 0
irtstr I
|s -^i
courr€a
0
|:[.r[|'.SlI
C IE O
OUI O
ito:i,l
lD--+<
Pl-<
ro-
ri
a
*rGll"J
.lrfift
d
:ry-lI
."1::.;"'l
z
4
I
A
6Al€ r
\ t1/
oul
clx !
I
a
J
t
crx 2
coutlEn
UOED
Y
GAt€ 2
out 2
231244-4
Flgure3. BlockDlagramShowlngDataBus
Buffer and Read/WrlteLoglc Funcilons
231244-5
READ/WRITE
LOGIC
The Read/WriteLogicacceptsinputsfromthe system busandgenerates
controlsignalslor the other
functionalblocksof the 82C54.A1 and A9 select
oneof the threecount€rsor the ControlWordReoister to be readfrom/writteninto.A "low" on theFD
inputtellsthe 82C54that the GPllis readingone of
the counters.A "low" on the WF input t-ettstne
82C54that the CPUis writingeithera ControlWord
or an initialcount.BothRD anOWF'arequalified
by
G; FE andWFiare ignoredunlessthe 82C54ha;
beenselectedby holdingG tow.
Flgure 4. Block DlagramShowlng ControtWord
Reglster and Counter Funcflons
couNTER 0, COUNTER1, COUNTER2
These three functionalblocks are identicalin operation, so only a singleCounterwill be described.The
internalblock diagramof a singlecounteris shown
in Figure5.
The Gountersare fully independent.Each Gounter
may operate in a different Mode.
The Control Word Registeris shown in the figure; it
is not part of the Counter itself, but its contents determine how the Counter operates.
3-85
int€f
82C54
storedin the CR and latertranslerredto the CE.The
Control Logic allows one registerat a time to be
loaded from the internal bus, Both bytes are transferred to the GE simultaneously.
CRy and CRL are
cleared when the Counter is programmed.In this
way, if the Counterhas been programmedfor one
byte counts (eithermost significantbyt€ only or least
significantbyte only) the other byte will be zero.
Note that the CE cannot be written into; whenevera
count is written,it is writteninto the CR.
The ControlLogicis also shownin the diagram.CLK
n, GATE n, and OUT n are all connectedto the outside world throughthe ControlLogic.
82C54SYSTEMINTERFACE
231244-6
Flgure5. IntemalBlockDlagramof a Gounter
The status register, shown in the Figure, when
latched,containsthe cunent contents of the Control
Word Regisler and status of the output and null
count flag. (See detail€dexplanationof the ReadBack command.)
The actualcounterlslabelledCE (for "CountingElement"). lt is a 16-bitpresettablesynchronousdown
counter.
The82C54is treatedby the systemssottwareas an
anayof peripherall/O ports;threeare countersand
the lourth is a controlregisterfor MODEprogramming.
Basically,
the selectinputsAo,A1connectto the Aq,
A1addressbussignalsof the CPU.The CScan be
dcdveddirectlyfromthe addressbus usinga linear
selectmethod.Or it can be connectedto the output
of a decoder,suchas an lntel 8205for largersystems.
OLy and OLs are two 8-bit latches. OL stands lor
"Output Latch"; the subscripts M and L stand for
"Most significantbyte" and "Least significantbyte"
respectively.Both are normally relened to as one
unit and calledlust OL. Theselatchesnormally"follow" the CE, but if a suitable Counter Latch Command is sent to the 82C54,the latches"latch" the
present count until read by the CPU and then return
to "following" the CE. One latch at a tameis enabled
by the counter's Control Logic to drive the internal
bus. This is how the 16-bitCountercommunicates
over the 8-bit internal bus. Note that the cE itself
cannot be read; whenever you read the count, it is
the OL that is beingread.
Similarly,there are two 8-bit registerscalled CRy
and CRs (for "Count Register").Both are normally
referredto as one unit and called lust CR. When a
new count is written to the Counter, the count is
3-86
lr
&
EE
' corrxtci
0r2
bD,
atc..
oounrr
ollt
ctr'
oourrEl
'ot
t ol?E cu'
231244-7
Flgure6.82C54SystemInterface
inbf
82C54
OPERATIONAL
DESCRIPTION
Programmingthe 82C54
General
Gountersare programmedby writinga ControlWord
and then an initialcount.The controlwordformatis
shown in Figure7.
After power-up,the state of the 82C54is undefined.
The Mode, count value,and output of all Gounters
are undefined.
How each Counteroperalesis determinedwhen it is
programmed.Each Counter must be programmed
beforeit can be used.Unusedcountersneed not be
programmed.
All ControlWords are writteninto the ControlWord
Register,whichis selectedwhen 41, Ao : 11.The
ControlWord itself specifieswhich Counteris being
programmed.
By conlrast,initialcountsare writteninto the Counters, not the ControlWord Register.The 41, As inputs are used to select the Counter to be written
into.The format of the initialcount is determinedby
the ControlWord used.
ControlWord Format
A1,As:11 6:0
RD-:1 WFi:0
D7
D5
sc1 sc0
SC -
D5
Da
D3
D2
RW1 RW0 M2
D1
De
M 1 MO BCD
M - MODE:
M2
ill
Select Counter:
scl
sco
0
0
SelectCounter0
0
0
0
Mode0
0
1
Select Counter1
0
0
I
Mode 1
1
0
SelectCounter
2
X
1
0
Mode2
1
1
Read-BackCommand
(See Read Operations)
X
1
1
Mode3
1
0
0
Mode4
1
0
1
Mode 5
RW- Read/Wrlte:
RWl RWo
0
0
MO
BCD:
CounterLatch Command(see Read
Operations)
0
0
1
Read/Writeleastsignificantbyte only.
1
0
Read/Writemost significantbyte only.
1
1
Read/Writeleastsignificantbyte first,
then most significantbyte.
1
BinaryCounter16-bits
BinaryCodedDecimal(BCD)Counter
(4 Decades)
NOTE: Don'l care bits (X) should be 0 to insure
compatibilitywith future lntel products.
Figure7. GontrolWordFormat
3-87
intef
82C54
structionsequenceis required.Any programming
thatlollowsthe conventions
sequence
aboveis acceptable,
WriteOperations
procedure
The programming
for the 82C54is very
flexible.Onlytwo conventions
needto be rememA nqwinitialcountmaybe writtento a Counterat
bered:
any time without affecting the Counter's pro1) For each Counter,the ControlWord must be
grammed
Modein anyway.Counting
willbeatfected
writtenbeforethe initialcountis written.
in the Modedefinitions.
Thenewcount
as described
2) The initialcountmustfollowthe countformat mustfollowthe programmed
countformat.
specifiedin the ControlWord (leastsignificant
byteonly,mosisignificant
byteonly,or leastsiglf a Counteris programmed
to read/writetwo-byt€
nificantbyteandthenmostsignificant
byte).
counts,the followingprecaution
applies:A program
mustnot transfercontrolbetweenwritingthe first
Since the ControlWord Registerand the three
andsecondbyteto anotherroutinewhichalsowrites
Countershaveseparateaddresses(selectedby the
intothat sameCounter.Othenrise,
the Counterwill
Ar, Ao inputs),andeachControlWordspecifies
the
be loadedwithan incorrectcount.
Counterit appliesto (SC0,SC1bits),no speciatinControlWordLSBof countMSBof countControlWordLSBof countMSBof countControlWordLSBof countMSBof count-
Counter
0
Counter0
Counter
0
Counter1
Counter1
Counter1
Counter
2
Counter2
Counter
2
ControlWordCounterWordControlWordLSBol countLSBof countLSBof countMSBof countMSBof countMSBot count-
Counter0
Counter1
Counter2
Counter2
Count€r1
Counter
0
Counter
O
Counter1
Counter2
A1
1
0
0
1
0
0
1
1
1
As
1
0
0
1
1
1
1
0
0
A1
1
A6
1
't
1
1
1
0
1
0
0
1
0
'l
0
0
0
0
1
GontrolWordControlWord
ControlWord
LSBof countMSBof countLSBof countMSBof countLSBof countMSBof count-
A1
11
11
11
10
10
01
01
00
00
Ao
Counter2
Counter1
Counter0
Counter
2
Counter2
Counter1
Counter1
Counter0
Counter0
ControlWordControlWord
LSBof countControlWordLSBof countMSBof countLSBof countMSBof countMSBof count-
A1
11
11
01
11
00
01
10
00
10
Ao
Gounter1
Counter0
Counter1
Counter
2
Counter0
Counter1
Counter2
Counter0
Counter2
NOTE:
In all four examples,all countersar€ programmedto read/writetwo-byt€@unls.
These are only four of many possibleprogremmings€quenc€s.
Figure8. A FewPosslbleProgrammlngSequences
ReadOperations
It is often desirable to read the value of a Counter
withoutdisturbingthe countin progress.This is easily done in the 82C54.
There are three possible methodsfor readingthe
counters: a simple read operation, the Counter
Latch Command,and the Read-BackCommand.
Each is explainedbelow. The first method is to perform a simple read operation.To read the Counter,
which is selectedwith the A1, A0 inputs,the CLK
input of the selected Counter must be inhibited by
using either the GATE input or eriternallogic. Otherwise, the count may be in the process o{ changing
when it is read,givingan undefinedresult.
3-88
intet
82C54
grammingoperationsof other Countersmay be insertedbetweenthem.
COUNTERLATCH COMMAND
The secondmethoduses the "CounterLatch Command". Likea ControlWord,this commandis written
to the Control Word Register,which is selected
when 41, Ao : 11. Also like a ControlWord,the
SCO,SC1 bits selectone of the three Counters.but
two other bits,D5 and D4, distinguishthis command
from a Gontrol Word.
Another feature of the 82C54 is that reads and
writesof the same Countermay be interleaved;for
example,if the Counteris programmedfor two byte
counts,the followingsequenceis valid.
'1.
Read teastsigniticantbyte.
2. Write new least significantbyte.
3. Read most significantbyte.
4. Write new most significantbyte.
A r , A o : 1 1 ;F S : 0 ; F D : 1 ; W F : O
D5
D5 Da D3 D2 D1 De
sc1 sc0 0 0 X X X X
9t
lf a Counteris programmedto readlwrite two-byte
counts,the followingprecautionapplies;A program
must not transfer control between reading the first
and secondbyteto anotherroutinewhichalso reads
from that same Counter.Othenrvise,an incorrect
counl will be read.
SC1, SCO- specifycounterto be latched
scl
sco
Counter
0
0
1
1
0
1
0
1
0
READ.BACKCOMMAND
1
2
Read-BackCommand
The third method uses the Read-Backcommand.
This commandallows the user to check the count
value, programmedMode, and cunent state of the
OUT pin and Null Count llag of the selectedcounte(s).
D5,D4- 00 designatesCounterLatchCommand
X - don't care
The commandis writteninto the ControlWord Register and has the format shown in Figure 10. The
commandappliesto the countersselectedby setting their correspondingbits D3,D2,D1: 1.
NOTE:
Don'tcarebits (X) shouldbe O to insurecompatibility
withfutureIntelproducts.
Figure 9. Gounter Latching Command Format
The selectedCounter'soutputlatch(OL)latchesthe
count at the time the Counter Latch Commandis
received.This countis hetdin the latchuntilit is read
by the CPU (or until the Counteris reprogrammed).
The count is then unlatchedautomaticaliyand the
OL returnsto "following"the countingelement(CE).
This allows reading the contents of the Counters
"on the fly" withoutaffectingcountingin progress.
MultipleCounterLatch Commandsmay be used to
latch more than one Counter.Each latched Counter's OL holdsits count untilit is read.CounterLatch
Commandsdo not affect the programmedMode of
the Counterin any way.
lf a Counter is latched and then, some time later,
latched again before the count is read, the second
CounterLatchCommandis ignored.The count read
will be the count at the time the first CounterLatch
Commandwas issued.
With either method,the count must be read according to the programmedformat; specifically,if the
Counter is programmed for two byte counts, two
bytes must be read. The Wo bytes do not have to be
read one right after lhe other; read or write or pro-
A0,At:it
CS--O FD:i
WF:O
D5:0 = Latch count of selectedcounter(s)
Da:0 : Latch statusol selectedcounter(s)
D3: 1 : Select counter2
D2: 1 : Selectcounler 1
Dr: 1 : Selectcounter0
Dq: Reservedfor futureexpansion;must be 0
Figure10.Read-Back
GommandFormat
The read-backcommandmay be used to latch multip]l,gg_unter output tatches (OL) by setting the
COUNT bit D5=0 and selectingthe desirediounte(s). This single commandis functionallyequivalent to several counter latch commands, one for
each counterlatched.Each counter'slatchedcount
is held until it is read (or the counter is reprogrammed).That counter is automaticallyunlatched
when read, but other counters remain latched until
they are read.lf multiplecountread-backcommands
are issuedto the same counterwithoutreadingthe
3-89
inbf
82C54
count,all but the first are ignored;i.e.,the count
whichwill be readis the countat the timethe first
read-back
command
wasissued.
Theread-back
mayalsobe usedto latch
command
statusinformationof selectedcounter(s)by setting
mTG
bit D4:0. Statusmustbe tatchedto be
read;statusof a counteris accessed
by a readfrom
thatcounter.
THISACTION:
A. Writoto th€ control
rI
woror€glsler:(
B.
- Writeto lhe count
GAUSES:
C. Newcountis loadecl
inroGE(CR+ CE);
Nullcount= 0
r"gir1"i(cnil,j
Nullcount: 1
Nullcount=1
ttl Only the counterspecifiedby the controlword will
have its null count s€l to 1. Null count bits of other
countersare unatfected.
l2l tt ttre counter is programmsdfor two-byte counts
(least significantbyte lhen most significantbyte) null
count gogs to 1 when the secondbyte is wrinen.
Thecounterstatusformatis shownin Figure11.Bits
D5 throughD0 containthe counter'sprogrammed
Modeexactlyas writtenin the last ModeControl
Word.OUTPUTbit D7 containsthe currentstateof
the OUT pin. This allowsthe us6rto monitorthe
counter'soutputvia software,possiblyeliminating
somehardware
froma system.
Flgure12.NullCountOperatlon
lf multiplestatuslatchoperations
of the counte(s)
aregerlormedwithoulreadingthe status,all butthe
firstare ignored;i.e.,the statusthat will be readis
the statusof the counterat the timethe first status
read-back
wasissued.
command
D7 1 0:
D610 :
Ds-Do
Oul Pin is 'l
OutPinis0
N u l lc o u n t
Countavailablefor reading
CounlerProgrammedMode (See Figure7)
Figure11.StatusByte
NULL COUNTbit DOindicateswhen the last count
written to the counter register(CR) has been loaded
into the countingelement(CE).The exact time this
happensdependson the Modeof the counterand is
describedin the Mode Definitions,but untilthe count
is loadedinto the countingelement(CE),it can't be
read from the counter. It the count is latchedor read
before this time, the counl value will not reflectthe
new count just written. The operation of Null Count
is shown in Figure12.
Command
D7 D5 D5 Da D3 D2 D1 Ds
Both count and statusof the selectedcounter(s)
may be latchedsimultaneously
by setting both
COUNTand STATUSbits D5,D4:0. This is functionallythe sameas issuingtwo separateread-back
commands
at once,andthe abovediscussions
apply herealso.Specifically,
if multiplecountand/or
statusread-backcommandsare issuedto the same
counter(s)
withoutanyintervening
reads,all butthe
firstare ignored.
Thisis illustrated
in Figure13.
lf bothcountandstatusol a counterarelatched,the
firstreadoperationof that counterwill returnlatched
status,regardlessof which was latchedfirst. The
next one or two reads(dependingon whetherthe
counteris programmed
for one or two type counts)
returnlatchedcount.Subsequentreadsreturnunlatchedcount.
DescrlPtlon
Results
I
1
0
0
0
0
1
0
Readbackcountandstatusof
Counter0
Countandstatuslatched
for Counter0
1
1
I
0
0
1
0
0
Read back statusof Counter1
Status latchedfor Gounter1
1
a
1
0
1
{
0
0
Read back status of Counters2, 1 Status latchedfor Counter
2, but not Counter1
1
1
0
1
1
0
1
1
0
0
0
1
0
0
0
0
1
1
1
0
0
0
1
0
Readbackcountof Counter2
Readbackcountandstatusof
Counter1
Readbackstatusof Counter1
I
I
Countlatchedfor Counter2
Countlatchedfor Counter1
butnotstatus
Command
ignored,
status
alreadylatchedfor Counter1
Figure13.Read.BackCommandExample
3-90
82C54
F
RD WR
1
0
1
0
1
0
1
0
0
1
Ar
A6
0
0
0
1
1
0
1
1
0
0
WriteintoCounter
0
WriteintoCounter1
WriteintoCounter
2
WriteControlWord
ReadfromCounter
0
0
1
0
1
Readfrom Counter1
0
1
1
0
0
0
1
1
1
'l
X
X
0
1
1
X
X
X
X
ReadfromCounter
2
No-Operation
(3-State)
No-Operation
(3-State)
0
0
0
0
0
0
0
This allowsthe countingsequenceto be synchronized by_sotnrare.
Again,OUT does not go high until N
+ 1 CLK pulsesafter the new count of N is written.
lf an initialcount is writtenwhile GATE = 0, it will
still be loadedon the next CLK pulse.When GATE
goes high,OUT will go high N CLK pulsestater;no
CLK pulse is neededto load the Counteras this has
alreadybeen done.
No-Operation(3-State)
Flgure14.Read/WrlteOperailonsSummary
l . l - l * | " I I | 3| ! | i I s l : : l i 5 l
The followingare definedfor use in describing
the
op€rationof the B2CS4.
CLKPULSE:
a risingedge,thena fallingedge,in
thatorder,of a Counter,s
CLKinput.
TRIGGER:a
risingedgeof a Counter's
GATEinput.
COUNTER
LOADING:the
transferof a countfrom
ths CR to the CE (referto
the "FunctionalDescription")
CW. l0
Lal. t
l-l'.l-1., l3 | tl! l: lt ls l:Il
MODE0: INTERRUPT
ON TERMTNAL
COUNT
yod.e9 is.typicailyusedfor eventcounting.Atterthe
ControlWordis written,OUTis initiallylo-w,andwill
remainlowuntiftheCounter
reacheszero.OUTthen
goeshighand remainshighuntila newcountor a
new Mode0 ControlWordis writteninto the Coun_
ter.
GATE: 1 enablescounting;GATE: 0 disables
counting.
GATEhasno effecton OUT.
AftertheControlWordandinitialcountarewrittento
a Counter,
theinitialcount
willbe loadedon the next
CLKpulse.ThisCLKpulsedoesnotdecrement
the
count,so for an initialcountof N, OUTdoesnot go
highuntilN + 1 CLKpulsesafterthe initialcountis
written.
lf a new countis writtento the Counter,it will be
loadedon the nen CLKpulseandcounting
willcontinuefromthe newcount.lf a two-bytecountis written,the folfowinghappens:
1) Writingthefirstbytedisabtes
counting.
OUTis set
low immediately
(noclockpulserequired).
2) Writingthe secondbyteallowsthe newcounrto
be loadedon the nerl CLKpulse.
3-91
l-l,,l- l- li lt I il : lt ls l#l
2g1244-8
NOTE:
The FollowingConventionsApply To Alt Mode Trmrng
Diagrams:
1. Counters are programmedfor binary (not BCD)
countingand tor Reading/Writingleast signiiicantbge
(LSB)only.
2. The counteris alwaysselected(G alwavslow).
3. CW stiandsfor "ControlWord"; CW - iO meansa
conlrol word ol 10, hex is wdttento the counter.
4. LSB standsfor "Least SignificantByte" ol count.
5. Numbersbelowdiagramsare countvalues.
I ne towernumberis the leastsignificantbyte.
The upper numberis the mostlignificanf byte. Since
the counter is- programmedto Read/Write LSB onty,
the most significantbyte cannot be read.
N standslor an undefinedcount.
Verticallines show transitionsbetweencount values.
Figure15.Mode0
intef
82C54
I'ODE 1: HARDWARERETRIGGERABLE
ONE.SHOT
OUTwillbe initiallyhigh.OUTwillgo low on the CLK
pulsefollowinga triggerto beginthe one-shotpulse,
and will remainlow until the Counterreacheszero.
OUT willthengo highand remainhighuntiltheCLK
pulse after the next trigger.
After writingthe ControlWord and initialcount, the
Counter is armed. A trigger results in loading the
Counterand settingOUT low on the next CLK pulse,
thus startingthe one-shotpulse.An initialcountof N
will resultin a one-shotpulse N CLK cyclesin duration. The one'shot is retriggerable,hence OUT will
remain low for N CLK pulsesafter any trigger.The
one-shotpulsecan be repeatedwithoutrewritingthe
same countinto the counter.GATEhas no effecton
OUT.
lf a new countis writtento the Counterduringa oneshot pulse,the currentone-shotis not affectedunless the Counter is retriggered.In that case, the
Counteris loadedwith the new count and the oneshot pulse continuesuntilthe new count expires.
MODE2: RATE GENERATOR
This Mode functionslike a divide-by-Ncounter.lt is
typiciallyused to generatea Real Time Clock inter'
rupt.OUT will initiallybe high.Whenthe initialcount
has decrementedto 1, OUT goes low for one CLK
pulse. OUT then goes high again, the Counterreloads the initialcount and the processis repeated.
Mode 2 is periodic;the same sequenceis repeated
indefinitely.For an initialcount of N, the sequence
repeatsevery N CLK cycles.
GATE : 1 enablescounting;GATE = 0 disables
counting.It GATE goes low duringan outputpulse,
OUT is s€t high immediately.A trigger reloadsthe
Counterwith the initialcount on the nexl CLK pulse;
OUT goes low N CLK pulsesafter the trigger.Thus
the GATE input can be used to synchronizethe
Gounter.
After writing a Control Word and initial count, the
Counterwill be loadedon the next CLK pulse.OUT
goes low N CLK Pulsesafter the initialcount is written. This allows the Counterto be synchronizedby
sottware also.
FT
r-I
clt
clx
gATE
oll:
OU?
out
l.l"l
xlxlxl:
lt lil 3|ff|3 lll
WT
wr
cLt
ctx
oAlt
oltE
our
l..i- l" l.l! l: lt l! lt lilS I
OUT
l.l- | "l*l* l3 I: lt lil: lt l3 |
Cg. t.
L3tra
LSl.5
- grt
CWrt2
Lsac,
L3!ra
cLl(
FT
olrE
clx
oul
cllc
l'.l.l.l.
i: l3l: l: ll l: l: I
231244-10
oul
l- l" i'ir
jx i I i l i3 iFil::l: l: I
23',t244-9
Figure 16.Mode 1
NOTE:
A GATEtransitionshouldnot occurone clockoriorto
terminal
count.
Figure 17.Mode 2
int€f
82C54
Wdtinga newcountwhilecountingdoesnot atfect
the cunentcountingsequence.lf a triggeris receivedafterwritinga newcountbut beforethe end
of thecurrentperiod,theCounter
willbe loadedwith
the newcounton the nsxtCLKpulseandcounting
will continuefrom the new count.Othen,ise,the
newcountwill be loadedat the end of ihe cunent
countingcycle.ln mode2, a COUNTof 1 is illegal.
OUT will be high for (N + 1)/2 countsand low lor
(N -1)/2 counts.
9I
ctr
olra
OI
MODE3: SQUAREWAVEMODE
l"l"l*l"li
!!oqe 3 is typicallyusedfor Baudrategeneration.
Mode3 is similarto Mode2 exceptforthedutycycle
of OUT.OUTwiltinitiailybe higfr.Whenhatfins initialcounthasexpired,
OUTgoeslowfor theremainder of the count.Mode3 is periodic;
the sequence
aboveis repeatedindefinitely.
An initialcountof N
resultsin a squarewavewith a periodof N CLK
cycles.
Cl.
Evencounts:OUTis initiallyhigh.Theinitialcount
is
loadedon one CLKpulseandthenis decremented
by two on succeeding
CLKpulses.Whenthe count
expiresOUTchangesvalueand the Counteris reloadedwiththe initialcount.The aboveprocessis
repeatedindefinitely.
Odd counts:OUT is initiattyhigh.The initiatcount
minusone (anevennumber)is loadedon one CLK
pulseandthenis decremented
by two on succeeding CLKpulses.OneCLK gulseafterthe countexpires,OUT goes low and the Counteris reloaded
with the initialcount minusone. Succeeding
CLK
pulsesdecrement
the countby two.Whenthecount
expires,OUT goes highagainand the Counteris
reloadedwiththe initialcountminusone.Theabove
processis repeatedindefinitely.
So for odd counts,
!
orlE
dl
r|
3!t
ottl
oul
Afterwritinga ControlWordand initialcount,the
Counterwill be toadedon the nextCLKpulse.This
allowsthe Counterto be synchronized
by sottware
also.
Mode3 is implemented
as follows:
lll.
cti
GATE= 1 enablescounting;GATE: O disables
counting.
lf GATEgoeslowwhiteOUTis low,OUTis
set highimmediately;
no CLK pulseis required.A
triggerreloadsthe Counterwith the initialcounton
the nextCLK pulse.Thusthe GATEinputcan be
usedto synchronize
the Counter.
Writinga new countwhilecountingdoesnot atfect
the curent countings€guence.lf a triggeris receivedafler writinga newcountbut beforethe end
of the currenthalf-cycleof the squarewav€,the
Counterwill be loadedwith the new counton the
nextCLKpulseand countingwill continuefromthe
newcount.Othenvise,
the newcountwill be loaded
at the endof the currenthalf-cycle.
ia
9r
l.l.l'l.lll:l
:ltl:l:l
:l: l:l :l
231244-11
NOTE:
A GATEtransition
shouldnot occurone clockpriorto
terminalcount.
Figure 18. Mode 3
ilODE 4: SOFTWARETRtccERED STROBE
OUT will be initialtyhigh.When the initiatcount expires,OUT will go low for one CLK pulse and then
go highagain.The countingsequenceis .,triggered"
by writing the initial count.
GATE : 1 enablescounting;GATE = 0 disables
counting.GATE has no etfect on OUT.
Atler writing a Control Word and initial count, ihe
Counterwill be loadedon the next CLK pulse.This
CLK pulse does not decrementthe couni, so for an
initial count of N, OUT does not strobe low until
N + 1 CLK pulsesafter the initialcount is written.
lf a new count is written during counting,it will be
loadedon the next CLK pulseand countingwill con.
tinue from the new count.lf a two-bytecount is written, the followinghappens:
3-93
intef
82C54
1) Writingthe first byte haSno effect on counting.
2) writing the secondbyte allowsthe new count to
'
cLKpulse.
onthenext
beroa?ed
by
This allowsthe sequenceto be ..ret1ggered"
software.OUTstrobeslow N*1 CLKpulsesafter
the newcountof N is written.
After writingthe ControlWord and initialcount,the
will not be loadeduntilthe cLK pulseaftera
."-?-T:t
ffii"ff:: li::
Xitffi:'.:^i:,?h*,r,0,,*i""oor""itoiil,
strobelowuntilN+ 1 cLK pulsesattera trigger.
A triggerresultsin theCounterbeingloadedwith.the
initialcounton the next CLK pulse.The counting
sequenceis retriggerable.OUT will not strobe low
for N * 1 CLK pulsesafter any trigger.GATE has
no effecton OUT.
m
cLx
OATC
our
o lFtl;rlFrl
0lFrlFElrDl
thecurrent
lf a newcountis writtenduringcounting,
countingsequencewill not be atfected.lf a trigger
occursafterthe newcountis writtenbut beforethe
currentcountexpires,the Counterwill be loaded
with the new count on the next CLK pulse and
willcontinuefromthere.
counting
m
FI
ctx
c(r
ol?r
oaft
out
l"l.l ,l.lll
olololololrrl
3l3l2lrl0lFFl
La!r2
9I
fl
cLx
cLt
oA?l
OATC
our
our
l. l,.l,.l"l3 | :l:l:
lt l: lffl
l"l. l.l*l*l,l:
231244-12
Ct . rl
Figure 19.Mode 4
131.3
ltl
I :l ll ll llslrll
* 5
*-r
cLt
MODE 5: HARDWARETRIGGEREDSTROBE
(RETRIGGERABLE)
6ltt
OUT will initiallybe high. Countingis triggeredby a
risingedge of GATE.When the initialcounthas expired,OUT will go low for one GLK pulse and then
go high again.
oul
lr rr rl r l t tr2 r ll rl o l rl trt ; I ll 3xr . l l o I o l o I o l r r l r : l
o ; o I
231244-13
Flgure20.Mode5
3-94
inbr
82Cs4
Operation Common to All Modes
Programmlng
1) Initiates
counting
2) Resetsoutput
after next
clock
Flgure21.Gatepln OperailonsSummary
MODE Mll'l
MAX
COUNT
couitT
0
1
0
1
1
0
2
2
0
3
2
4
1
0
0
NOTE:
0 is eguivalentto 216 lor binary countingand .104for
BCD counting
Figure22.Minlmumand MaxlmuminlilalCounts
Whena ControlWordis writtento a Count€r,
afl
Control
Logicis immediately
resetandOUTgoesto
a knowninitialstate;noCLKpulses
arerequired
for
this.
GATE
The GATEinputis alwayssamptedon the rising
edgeol CLK.In Modes0, 2,9, and4 theGATEinpui
is levelsensitive,
andthe logiclevelis sampledon
the risingedgeof GLK.In Modes1,2, g, and5 the
GATEinputis rising-edge
sensitive.
In theseModes,
a risingedgeof GATE(trigger)setsan edge-sensitivellip-flop
in theCounter.
Thisflip-flopis tien sampledon the nextrisingedgeof CLK;ifre nip-ttopis
resetimmediately
afterit is sampled.In this way,a
triggerwill be detectedno matterwhenit occurH
highlogiclevetdoesnot haveto be maintained
until
the next risingedgeof CLK.Notethat in Modes2
and3, the GATEinputis bothedge-andlevel_sensitive.In Modes2 and 3, if a CLKsourceotherthan
the systemclock is used,GATEshouldbe pulsed
immediately
followingWF of a newcountvalue.
COUNTER
New countsare loadedand Countersare decre_
mentedon the fallingedgeof CLK.
fhe largeg!possibfeinitiatcountis 0; this is equiva_
fent to 216 lor binarycountingand 104 for BCD
counting.
The Counterdoesnot stopwhenit reacheszero.In
Modes0, 1,4, andS the Counter,.wrapsaround"to
the highestcount,eitherFFFFhexfor binarycountingor 9999for BCDcounting,
andcontinueicornt_
ing.Modes2 and3 areperiodic;the Counterreloads
itself with the initialcount and continuescounting
fromthere.
8255Programmable
PeripheralInterface
DataSheetReprint
I
intel"
82C55A
INTERFACE
PERIPHERAL
CHMOSPROGRAMMABLE
I
r
a
I
r
I ControlWord Read'BackCapabillty
I DirectBit Set/ResetCaPabllitY
J 2.5mA DGDriveGapabilltyon all l/O
Port Outputs
r AvallableIn 40-PinDIPand 44-PinPLCC
I AvailableIn EXPRESS
-Standard TemperatureRange
- ErtendedTemperatureRange
Compatiblewith all Inteland Most
Other Microprocessors
HaghSpeed,"Zero WaltState"
Operationwith 8 MHz8086/88and
8 0 18 6 /1 8 8
l/O Pins
24 Programmable
Low PowerCHMOS
CompletelyTTL ComPatlble
CHMOSversionof the industrystandard82554 generalpurpose
The Intel 82C55Ais a high-performance,
ft provides
programmablel/O devicewhichis designedfor use with all Inteland most other microprocessors.
of
operation.
in
3
maior
modes
groups
12
used
programmed
and
in
of
pins
2
whichmay be individually
Zq ltO
The 82C55Ais pin compatiblewith the NMOS8255Aand 8255A-5.
fn MODE 0, each groupof 12llo pins may be programmedin sets ol 4 and I to be inputsor outputs.In
to haveI linesof inputor output.3 of the remaining4 pinsare used
MODE 1, each gto,ipmly be programmed
bus configuratlon.
for handshakingand intenuplcontrolsignals.MODE2 is a strobedbi-directional
provides
low powerconsumption
The 82C55Ais fabricatedon Intel'sadvancedCHMOSlll technologywhich
product.
82C55A
is availablein 4Gpin
The
NMOS
greater
pertormance
than
the
equivalent
with
equalto or
DIP and 44-pinplasticleadedchip carrier(PLCC)packages.
re!r!!l.!trE
tts.l
E
DI
D2
ut
rc
0a
E
r
o
tttttrRitii
aqcB4t.E
231256-31
*
!2C55
Iri
r.
,t
231256-1
Flgure 1.82C55ABlock Dlagram
a12fi-2
Flgure2.82C55APlnout
E[agramsare for fln relerene only.Package
sizes are not to soal€.
g-124
S.ddnb.t tea7
Ordrr llunrbrr: 2ll | 23E{a
82C5sA
Table1.PlnDescrlpilon
Symbol
PAg-o
HT
PlnNumber
Dlp
PLCC
1-4
2-5
Type
vo
es
5
6
I
6
7
I
GND
7
I
Ar-o
8-9
9-10
I
vo
Nameand Functlon
PORTA, PINS0-3: Lowernibbleof an8-bitdataoutputtatch/
butferandan8-bitdatainputlatch.
READCONTROL:
Thisinputis towduringCPUreadoperations.
CHIPSELECT:
A lowonthisinputenables
theB2CSSA
to
respondto RE andWF signals.FT andWRareignored
otherwise.
SyatemGround
ADDRESS:
Theseinputsignals,
inconjunction
R-DandWF',
controllhe selectionof oneof thethreeportsor thecontrol
wordregisters.
Ar
A6
RD WE c-s InputOperatlon(Read)
0
0
0
I
0
PortA-DataBus
0
I
0
1
0
PortB-DataBus
I
0
0
1
0
PortC-DataBus
1
- DataBus
1
0
1
0
ControlWord
0
0
0
1
1
1
1
0
I
I
1
X
X
1
0
0
0
0
0
0
0
0
X
x
X
1
X
1
1
0
OutpulOperatlon(Wrtte)
DataBus. PortA
DataBus- PortB
DatraBus- PortC
DataBus- Control
DlsableFunctlon
DataBus-3-State
DataBus-3-State
PCt-t
10-13 11,13-15
PGo-g
14-17
't6-19
vo
PBoz
18-25
to
PORTB, PINS0-7: An 8-bitdataoutputtatch/bufierand an 8bit data inputbutfer.
SYSTEiIPOWER:* 5V powerSupply,
t/o
DATA BUS:Bi-directional,tri-statedata bus lines,connectedto
systemdata bus.
RESET:A highon thisinputclearsthe controlregisterand all
portsare set to the input mode.
RESET
35
20-22,
24-28
29
30-33,
35-38
39
WF
36
40
37-40
41 -44
vcc
26
Dz-o
27-34
PAz-q
NC
1,12,
23,34
PORTC, PINS4-7: Uppernibbteof an B-bitdataoutpuilatch/
butferand an 8-bitdata inputbutfer (no latch for input).This port
can be dividedinto two 4-bit ports underthe mode control. Each
4-bit port containsa 4.bit latch and it can be used for the control
signaloutputsand statussignalinputsin conjunctionwith ports
A and B.
PORTC, PINS0-3: Lowernibbleof port C.
WRITECONTROL:
Thisinputis lowduringCpUwrite
operations.
ato
PORTA, PINS4-7: Uppernibbleof an g-bitdataoutputlatch/
bufferand an 8-bitdata input latch.
NoConnect
3-125
int€f
82C554
DESCRIPTION
82C55AFUNCTIONAL
General
peripheralinterface
The 82C55Ais a programmable
sysdevicedesignedfor use in Intelmicrocomputer
tems. lts functionis that of a generalpurposel/O
componentto interfaceperipheralequipmentto the
microcomputersystembus. The functionalconfiguration of the 82C55Ais programmedby the system
softwareso that normallyno externallogicis necessary to interfaceperipheraldevicesor structures.
Data Bus Buffer
butferis usedto inter'
This 3-statebidirectionalS-bit
lace the 82C55A to the systemdata bus. Data is
transmittedor receivsdby the bufferuponexecution
of input or output instructionsby the CPU.Control
words and status informationare also trans{erred
throughthe data bus buffer.
Read/Wrlte and Control Loglc
The function of this block is to manageall of the
internal and external transfersof both Data and
Control or Status words. ft accepts inputs from the
CPUAddressand Controlbussesand in turn,issues
commandsto both of the ControlGroups.
Group A and Group B Gontrols
The functional configurationof each port is programmedby the systemssoftware.In essence,the
CPU "outputs" a controlword to the 82C55A.The
controlword containsinlormationsuch as "mode",
"bit set", "bit reset", €tc., that initializesthe functional configurationof the 82C55A.
Eachof the Controlblocks(GroupA and GroupB)
accepts"commands"from the Read/WriteControl
Logic, receives "control words" from the int€rnal
data bus and issuesthe propercommandsto its associatedports.
ControlGroupA - PortA and PortC upper(C7-C4)
ControlGroupB - PortB and PortC lower(C3-C0)
The control word registercan be both writtenand
read as shown in the addressdecodetable in the
pin descriptions.Figure6 shows the control word
format for both Read and Write operations.When
the controlwordis read,bit D7 willalwaysbe a logic
"1", as this impliescontrolword mode information.
Ports A, B, and C
The 82C55Acontainsthree8-bitports(A, B, and C).
All can be configuredin a wide varietyof functional
by the systemsoftwarebut each has
characteristics
its own specialfeaturesor "personality"to further
enhancethe powerand flexibilityof the 82C55A.
Port A. One 8-bit data outputlatch/butferand one
8-bit input latch butfer. Both "pull-up" and "pulldown" bus hold devicesare presenton Port A.
Port B. One 8-bit data input/outputlatch/but{er.
Only "pull-up" bus hold devicesare presenton Port
B.
Port C. One 8-bit data outputlatch/bufferand one
8-bit data input buffer (no latchlor input).This port
can be dividedinto two 4-bit ports underthe mode
control.Each 4-bit port containsa 4-bit latch and it
can be used for the control signaloutputsand status
signalinputsin conjunctionwith portsA and B. Only
"pull-up" bus hold devicesare presenton Port C.
for
See Figure4 for the bus-holdcircuitconfiguration
Port A, B, and C.
3-126
inbf
82C55A
r-6
f,
r$f r
?31256-3
Flgure3.82C55ABlockDlagramShowlngOataBusBufferandRead/WrltoGontrolLoglcFuncilone
EXTERTIAL
POtr !,c
Plll
illEnilAL
orT
ffi
'NOTE:
231256-4
Poil pins loadedwith morelhan A) pF capacitancemay not havetheirlogiclevel guaranteed tollowing a hardware reset.
Flgure 4. Port A, B, C, Bus-holdConliguration
3-127
intef
82C55A
DESCRIPTION
82C55AOPERATIONAL
nono
ooa{TnoL
Da
Mode Selection
Da
Dr
o.
Dt
D2
o!
Do
There are three basic modes of operationthal can
be selectedby the systemsoftware:
Mode 0 - Basic input/output
Mode 1 - Strobedlnput/output
Bus
Mode 2 - Bi-directional
/
610'!
\
roRT c |loi,Eil
r . ll?ttl
0. OUtrut
Whenthe reset inputgoes "high" all portswillbe set
to the inputmodewith all 24 port linesheldat a logic
"one" level by the internalbus hold devices(see
Figure 4 Note). After the reset is removod the
82C55Acan remainin the inputmodewith no additionalinitializationrequired.This eliminatesthe need
for pullup or pulldowndevicesin "all CMOS" de'
signs.Duringthe executionol the systemprogram,
any of the other modesmay be selectedby usinga
single output instruction. This allows a singls
82C55A to service a varietyof peripheraldevices
wilh a simplesoftwaremaintenanceroutine.
'ORT !
r. ltltw
0. OUTruT
root 3Et€ctlot
O. l|OOt 0
t. l|OO[ I
/
ctorr a
\
FORIC turttl
l. lltul
0. OUTruT
The modes for Port A and Porl B can be separately
defined,while Port G is dividedinto two portionsas
All of
requiredby the Fort A and Port B definitions.
the output registers,includingthe statusflip-flops,
will be reset wheneverthe modeis changed.Modes
may be combined so that their functionaldefinition
can be "tailored" to almost any l/O structure.For
instance;Group B can be programmedin Mode0 to
monitorsimple switch closingsor displaycomputational results, Group A could be programmedin
Mode 1 to monitora keyboardor tape readeron an
basis.
interrupt-driven
foir a
l.liruI
O. OUTrur
rcol ttlCcTrol
O.rEff0
Ol .rcOa t
rI.rol
,
rcOC *' ILAG
I . llgrlvt
231256-6
Flgure6.llode DeflnltlonFormat
ct
The modedefinitionsand possiblemodecombinationsmayseemconfusing
at firstbut aftera cursory
reviewof the completedeviceoperationa simple,
logicall/O approachwill surface.The designof the
82C55Ahastakenintoaccountthingssuchas efiivs PG
cientPCboardlayout,controlsignaldefinition
layoutand completefunctionalflexibilityto support
devicewith no extemallogic.
almostany peripheral
Such designrepresentsthe marimumuse of the
pins.
available
SlngleBlt Set/ResetFeature
Anyof the eightbits of PortC can be Set or Reset
This featurereusinga singleOUTputinstruction.
in Control-bas€d
ducessottwarerequiremsnts
applications.
Flgure5. BaslcModeDefinltlonsand8us
lnterface
WhenPortC is beingusedas status/controllorPort
A or B, thesebitscanbe setor resetby usinglh€ Bit
Set/Resetoperationjust as if theyweredataou{put
ports.
3-128
inbf
82C55A
Intemrpt Control Funcllons
oofrrolFro
q
or
1l
-T-
q
Qlo.
I
I
r
Dr
Dl
oc
!r sfT/itsal
l.ttr
O. iE3tT
OoftlT
crl
artsEL:cr
l6lTl-?TinEf.m
#
- l 0 l r l 0 , r t o l r l r0l lu
- l 0 l 0 J| | t r a t 0rl l I l ! r l
-FFldffif'Iffi
ltTsfY/lltE
0. ACTIYI
When the 82G55Ais programmedto operate in
mode 1 or mod€2, controlsignalsare providedthat
can be used as interruptrequest inputs to the CPU.
The interruptrequ€stsignals,generatedfrom port C,
can be inhibitedor enabledby setting or resetting
the associatedINTEflip-flop,usingthe bit set/reset
functionof port C.
This functionallowsthe Programmerto disallowor
allowa specificl/O deviceto interruptthe CPU without attectingany other devicein the interruptstruclure.
FLAo
INTEflip-flopdefinition:
231256-7
(BIT-SETFINTEis SET-Interrupt enabte
(BIT-RESETFINTEis RESET-lntemrpt disabte
Flgure 7. Blt Set/Reset Format
Note:
All Mask flip-flopsare automaticallyreset during
modeselectionand deviceReset.
3-129
int€t
82C55A
OperatlngModes
Mode 0 (Baalc Input/Output).This functionalconfigurationprovidessimple input and output operations for each of the three ports.No "handshaking"
is required,data is simplywrittsnto or read lrom a
specifiedport.
Definitions:
Mode0 BasicF'.rnctional
o Two 8-bil ports and two 4-bit ports.
o Any port can be inputor output.
a Outputsare latched.
. lnputsare not latched.
o 16 diflerentInput/Outputconfigurations
are possiblein this Mode.
231256-8
MODE0 (BASTC
OUTPUT)
231256-9
3-130
intef
82C55A
trODE0 Port Deflnltlon
B
A
D4
D3
D1
Dq
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
0
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
'l
'l
GROUPA
PORTC
PORTA
(UPPER)
GROUP
B
PORTC
PORTB
(LOWER)
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
#
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
1
2
3
INPUT
4
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
0
INPUT
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
5
OUTPUT
OUTPUT
INPUT
INPUT
6
7
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
8
9
10
11
12
13
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
14
15
itODE0 Conllgurations
cortto(
$orDrD.OrO,
D,
v|oio a2
Oa O!
O.
O!
Or
O,
Do
0
0
0
I
0
coa{TRotf,oRo ,l
o, Dr O! O.
O,
O,
Or
Oo
0
I
0
cor?eol nono tt
0
3-131
o lo,o
INPUT
INPUT
INPUT
INPUT
INPUT
intet
82C55A
MODE 0 Conflguratlons(Continued)
o.
Dr
Dt
Or
coxraoL iono i
D, Or O! D.
Oo
0
I
0
Or
Or
Oo
0
0!0
tar'\
,lr,$
tcrtcr
.cft<.
,c/co
4#o
,sae
6ralo
ronD a
cottnol
ioRo 16
oo{riol
0
Ot
oro.D5o.%orD,Do
r
oluloi'lololr
corrriol rolo D, D. O! D.
0
o
o
O,
D,
0
D,
r^/\
tAr2\
fcrac.
tCitc.
rc/r!
rcrrco
try\
tlr4So
coxltot *oeo arc
o, Da or D.
Do
I
0
0
0
D!
O,
o
o
Dr
Oo
0
,A/\
,A/r\
ttlit
rFcr
rgf+to
tct4c!
t!r.ttb
trr{s
coi{teot tonD all
o,
Dr
I
0
o!
Da o!
o!'lo
D,
or
Do
0
,^fa\
rqr\
EftGr
J+,/t4!
ElGc
ryco
t.'tr!
,.r'q
231256-11
3-132
82C55A
IIOOE0 ConflguraUonr(Continued)
or
ot
or
o.
D,
o,
|roro rla
oo||YRoL
o'Or\O.DrDrDrOo
ol
I
0
I
0
ttt
0
I
0
odrmlnoro.tt
oofttol iotDtt!
q%qo.Dtororoo
0
0
0
o
I
Opcratlngllodcr
UODE 1 (Strobed Input/Output).This tunctional
providesa meansfor transferring
l/O
conliguration
with
datato or froma specifiedport in conlunction
In mode1,PortA
signals.
strob€sor "handshaking"
and PortB use the lineson PortC to generateor
signals.
acceptthese"handshaking"
Mode1 BasicfunctionalDefinitions:
r TwoGroups(GroupA andGroupB).
o Eachgroupcontainsone8-bitdataportand one
4-bitcontrol/dataport.
o The8-bitdataport can b€ eitherinputor output
Bothinputsand outputsare latched.
o The4-bitportis usedtor controlandstatusof the
8-bitdataport.
3-133
intef
82C5sA
Input Control Slgnal Deflnltlon
ffi (StroOe Input). A "low" on this input loads
data into the inputlatch.
@fiYrot iotD
IrO.qo.
I rx?r I
Li_.i
IBF (lnput Bufler Full F/F)
A "high" on this outputindicatesthat the data has
been loaded into the inputlatch;in essence,an ac'
knowledgement.IBF is set by STB ingt being low
and is reset by the risingedgeol the RD input.
INTR (lnterrupt Request)
A "high" on this outputcan be usedto interruptthe
CPU when an input device is requestingservice.
INTR is set by the 5TB is a "one", IBF is a "one"
and INTEis a "one". lt is resetby the fallingedge ol
ffi. tfris Droceciureallows an input device to re'
quest service from the CPU by simplystrobingits
data into the port.
INTE A
Controlledby bit set/reset of PCa.
INTE B
Controlledby bit set/reset of PC2.
t312fi-13
Flgure 8. ilODE 1 InPut
2t1235-ra
Flgure9. IIODE1 (StrobcdInput)
3-134
inbf
82C55A
Outnrl ControlSlgnalDeflnltlon
6eF-(OutputBuflcr Full F/D. The6BF-outputwill
go "low" to indicatethat the CPUhas writtendata
outto thespecifiedport.TheoEF ff f willbe set by
the risingedgeof the WF inputand r€s€tby FeR
lnputbeinglow.
ACK-(AcknowledgeInput).A "low" on this input
informsthe82C55AthatthedatafromPortA or Port
B hasbeenaccepted.In essence,a responsefrom
the peripheral
deviceindicatingthat it hasreceived
the dataoutputby the cPU.
INTR(lnterruptReque3t).A "high"on thisoutput
can be usedto intenuptthe GPUwhenan output
devicehas accepteddatatransmittedby the CPU.
INTRis set whenAG is a "one",6EF is a "one"
andINTEis a "one".lt is resetby thefallingedgeof
wH.
f--r
I lNTt
I
LJ-,I
INTE A
Controlledby bit set/resetof PC6.
INTE B
Gontrolledby bit set/reset of PC2.
2312s6-15
Flgurcll.llOOE I (StrobedOutput)
3-135
inbf
82C5sA
Combinationsof MODE1
definedas inputor outputin Mode 1 to supporta wide varietyol strobed
Port A and Port B cbn be individually
l/O applications.
lAr'?\
rc'
fca
coa{rioL nono
tcr
4OtD:D.OrDrOrDo
El. r
lcr, r
t/o
tQ.r
l. lNtW
0. OUtrul
It
?trtt!
?qru!
tcr
frr.
7cz
i6r.
fco
ItrRr
ioRr ^ - lstForEDouttwl
toar a - tsrnolgD r,{2u?l
foar a - tttFolED rr{pull
roer I - tstFolEDourrurl
231256-17
Figure 12.Combinationsol ltlODEI
Operating Modes
Output Operatlons
MODE 2 (Strobed Bidlrectlonal Bus l/O).This
functional configurationprovidesa means for communicatingwith a peripheraldeviceor structureon a
single 8-bit bus for both transmittingand receiving
data (bidirectionalbus l/O). "Handshaking"signals
are providedto maintainproperbus flow disciplinein
a similar manner to MODE 1. Interruptgeneration
and enable/disablefunctionsare also available.
6BF (Output Buffer Full). The 6BF outputwill go
"low" to indicatethat the CPU has written data oul
to port A.
MODE 2 Basic FunctionalDefinilions:
. Used in Group A onty.
o One 8-bit,bi-directional
bus port (PortA) and a 5bit control port (Port C).
. Both inputs and outputsare lalched.
o The S-bit control port (Port G) is used loi control
and status for the 8-bit, bi-directionalbus Port
(Port A).
INTE 1 (Ihe INTE Flip-Flop Aasoclated wlth
OBT). Controlledby bit set/reset of PC5'
Bldirectional Bus l/O Control SlgnalDefinltion
INTR (lnterrupt Request). A highon this output can
be used to interruptthe GPUfor inputot ortpiiopJt'
ations.
AeK (Acknowledge).A "low" on this inputenables
the tri-strateoutput buffer of Port A to send out the
data.Oherwise,the outputbutler will be in the high
impedancestate.
Input Operations
.,'w"
on this input loads
STE *tro'e Input). A
data into the input latch.
IBF (lnput Bulfer Full F/F). A "high" on this output
indicatesthat data has been loaded into the inPut
latch'
INTE Flip'Flop Assoclated wlth IBD'
t[IE-^',,9,h"
controlled by bit set/reset of PGa'
3-136
intef
82C55A
ts:l
t'l|.ru?
0. OUt?Ut
loe? !
I . lil?U7
0. OUrruT
GROI' 3 fOOt
0, rODE0
r.rrcOEr
231256-1E
Flgure13.MODECohtrotWord
231256- 1I
Figure14.MODE2
oattFx'|
cturo uctt
DATA F'OI
rEn't{€iat
to ftcaa
tlcaa
OATAFft'I
to*rn
ilcrAL
Figure 15.itOOE 2 (Bidirectionat)
NOTE:
AnlsequencerynereWF'occursbeforeAfl, :@_STEoccursbeforeffi is permissible.
(INTR= IBFr Fiffi. ffi. n-D+ OEF. FiI-SKo fiffi r ffi;
3-137
int€f
82C55A
M O O E2 A N O M O D EO ( O U T P U T }
MOOE2 AND MOOEO IINPUT}
Ir|tir
ic:
r+r\
6i^
Er^
oot{tioL *oRD
DrDr\O.DrOrOtDo
D, Dr O! O. Dr D,
tc"
o-t^
fcr
E^
D! Oo
-!l|^
F-!^
t!Fe
6le
t/o
t,l)
MOOE2 ANO TIIODE1 IINPUTI
MOOE2 ANO MODE I IOUTPUTI
rc'
tc!
r+.rt
rlrlXl'.
lXltl0
tart\
fct
o-tr
rc'
c-t^
?c.
iE-r^
tca
E^
tC.
m^
E
.t^
rq
lF^
tcr
lfe
oa-F.
tg:
3t\
Eir
tc!
sr
t{lia
tc!
f,rrL
rqrq
tq,l!
231256-21
Flgure16.IIODE/4 Comblnations
3-138
intef
82C55A
ModeDeflnltlonSummary
MODEO
MODE1
IN
OUT
IN
OUT
PAo
PAr
PAz
PAs
PAr
PAs
PA6
PAz
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PBo
PBr
PBz
PBg
PBn
PBs
PBe
PBz
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PCo
PGr
PGz
Pcg
PCn
PCs
PCo
PCz
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
our
OUT
OUT
OUT
MODE2
GROUPA ONLY
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
INTRs INTRs
lBFs 6EFe
IN
IN
IN
IN
IN
IN
IN
IN
MODEO
ORMODE1
ONLY
vo
tlo
t/o
SrB-s Affis
INTBa INTRl
faA
vo
lBFa t/o
INTRa
stEl
lBFa
AffiA
OE-rg
vo Affin
vo oEFl
SpeclalMode Comblnatlon Conslderatlonr
Thereare severalcombinationsof modespossible.
For any combination,someor all ol the PortC lines
are usedfor controlor status.The remainingbitsare
e:her inputsor outputsas definedby a "Set Mode"
command.
Duringa read of Port C, the state of all the Port C
lines,exceptthe AGK and STB lines,will be placed
on the data bus. In place of the ACK-and ffi line
states,flag statuswill appearon the data bus in the
PC2, PC4, and PC6 bit positionsas illustratedby
Figure18.
Througha "Write Port C" command,only the PortC
pinsprogrammedas outputsin a Mode0 groupcan
be written.No other pins can be atfectodby a "Write
PortC" command,nor can the intenuptenableflags
be accessed. To write to any Port C output programmedas an output in a Mode 1 group or to
changeaninterrupt
enableflag,the"Set/ReselPort
G Bit" command
mustbe used.
Witha "Set/ResetPortC Bit"command.
anyPortC
lineprogrammed
as an output(including
lNiR, IBF
andOBF)canbe written,or an interrupt
enableflag
canbe eithersetor reset.PortC linesprogrammed
as inputs,includingAffi andSfE lines,aisociated
withPortC arenot atlectedby a "Set/ResetPortC
Writinglgthecoresponding
Bit" command.
PortC
bit positionsof the ACK and STB lines with the
"Set/ResetPort C Bit" commandwill atfect the
GroupA andGroupB intenuptenableflags,as illustratedin Figure18.
CurrentDrlveCapablllty
Anyoutputon PortA, B or C cansinkor source2.5
mA.Thisfeatureallowsthe82C55Ato directlydrive
Darlingtontype driversand high-voltagedisplays
thatrequiresuchsinkor sourcecurrent.
3-139
inbf
82C55A
INPUTCONFIGURATION
Ds
D2
D1
D5
Da
Beading Port C Status
D7 D5
In Mode 0, Port C transfersdata to or from the peripheraldevice.Whenthe 82C55Ais programmed
to
function in Modes 'l or 2, Port C generatesor accepts "hand-shaking"signalswiththe peripheraldevice. Readingthe contentsol PortC allowsthe pro
grammer to test or verify the "stalus" of each peripheral device and change the programflow accordingly.
De
t t O l t / O l I B F AI I N T E AI I N T R A
I INTEB
I I B F BI I N T R B
GBOUPA
D7
GROUPB
OUTPUTCONFIGURATIONS
D5 D5 D4 D3
92
D1
GROUPA
There is no specialinstructionto readthe statusinformationlrom Port C. A normalread operationof
Port C is executedto pertormthis function.
De
GROUPB
Figure17a.MODE1 StatusWordFormat
D7
D6
D5
Da
D3
D2
D1
Dg
Al INTEI I IBFAI|NTE2lINTRA
GROUPA
GROUPB
(Dellned By Mode 0 or Mode 1 S€lection)
Figure 17b.MODE2 Status Word Format
Interrupt EnableFlao
INTEB
INTEA2
INTEA1
Posltlon
Alternate Port C Pin Signal(Mode)
PC2
PC4
PC6
Ade (OutputMode1)orSTB9(lnputMode1)
STBa(lnputMode1 or Mocte
2)
AGr (OuiputMode1 or Mode2
Figure 18.Interrupt EnableFlagsIn Modes 1 and 2
3-140
inbf
82C55A
MAXIMUMRATINGS'
ABSOLUTE
UnderBias....0'Cto+ 70'C
AmbientTemperature
StorageTemperature ..- 65'Cto* 150'C
- 0.5to + 8.0V
SupplyVoltrage
...+ 4vto * 7V
OperatingVoltage
to + 6.5V
lnput.
.
.GND-2V
Voltage
onany
Voltage
onanyOutput. .GND-0.5Vto V66 + 0.5V
. . .1 Watt
PowerDissipation
'Notice: Slrsssesabove thoselisted under "Abso
lute MaximumRatings"maycauseparmanentddm'
age to the device. Thisis a sfress rating only and
functionaloperationof the deviceat these or any
otherconditionsabovethoseindicatddin the opera'
tionatsectionsof thisspecificationis not implied.Ex'
posure to absolutemaximumrating conditionsfor
extendedperiodsmayaffect devicereliability.
D.C.CHARACTERISTICS
T A = 0 ' C t o 7 0 ' C , V c c= + 5 V t 1 0 o / o , G N D : 0 V ( T l :
Symbol
Parameter
-40'C to * 85'C for ExtendedTemperture)
Mln
Max
Unlts
TestCondltlonr
Vt
lnputLow Voltage
-0.5
0.8
V
vrx
InputHighVoltage
2.0
Vcc
v
vol
OutputLowVoltage
0.4
V
Vox
OutputHighVoltage
Ir
lnputLeakageCunent
t1
pA
lorl
OutputFloat LeakageCurrent
r10
pA
loen
Darlington
DriveCunEnt
t2.5
(Note4)
mA
lpxl
Current
PortHoldLowLeakage
+50
+300
pA
lpxx
PortHoldHighLeakageCurrent
-50
-300
pA
lpxlo
Port Hold Low OverdriveCunent
-350
pA
Vggl:
lpxxo
Port Hold HighOverdriveCunent
+350
pA
V6g1 : 3.0V
l6s
V6g SupplyCunent
t0
mA
(Note3)
lccsa
VsgSupplyCunent-Standby
10
pA
VCC: 5.5V
VtN : VCCor GND
Porl Conditions
ll llP : Open/High
OIP : OpenOnly
With DataBus :
High/Low
Fs = High
Reset: Low
PureInputs:
Low/High
V
V
3.0
Vs6 - 0.4
l9g : 2.5 mA
loH : -2.5 mA
loH : - 100pA
Vlp = Vg6 to 0V
(Note1)
V11: Vg6 to 0V
(Note2)
PortsA, B, C
Rq1 = 500O
Vs1 : 1.7V
I{OTES:
1. PinsA1,no,CS,WFi,FiD,Reset.
2. DataBus;PortsB, C.
3. Outputsopen.
4. Limitoulpulcurrentto 4.0mA.
3-141
V9g1 = 1.0V
PorlA only
V9g1 : 3.0V
PortsA, B, C
0.8V
irttef
82C55A
CAPACITANCE
TA : 25oC,VCC:GND : 0V
Mar
Unlts
Test Condltlons
InputCapacitance
10
pF
l/O Capacitance
20
pF
plns
Unmeasured
returned
to GND
f" : 1 MHz(S)
Parameter
Symbo!
9N
Crro
llln
NOTE:
5. Samplednot 10006tesled.
A.C. CHARACTERISTICS
TA : 0otO 70'C, VCC: +5V t10o/o,GND = 0V
TA : -40'C to +85'C for ExtendedTemperature
BUS PARAMETERS
BEAD CYCLE
Symbol
82C554-2
Parameter
Mln
Unlts
llax
ten
AddressStableBeforeFD J
0
ns
tnl
AddressHotdTimeAtterRD-|
0
ns
tnn
RDPulseWidth
150
ns
tRo
DataDelayfromFD.f
tor
tnv
FE t to DataFloating
Recovery
TimebetweenFDIWF
10
120
ns
75
ns
Teat
Gondltlons
ns
200
WRITECYCLE
Symbol
82C55A.2
Unttr
Tcst
Condltlonr
PortsA & B
20
ns
ns
ns
Parameter
tln
tRw
AddressStableBeforeWF'J
0
twn
AddressHoldTimeAtterWF f
20
tar
tww
WHPulsewidth
100
ns
tow
DataSetupTimeBeforeWFif
100
two
DataHoldTimeAfterWHf
30
ns
ns
ns
30
3-142
PortC
PortsA & B
PortC
82C55A
OTHERTIMINGS
Slmbol
ilax
Unltr
Condltlonr
350
ns
82C55A-2
Parameter
illn
lwe
WR: l toOutput
tn
PeripheralDataBeforeRD
0
ns
hn
Peripherat
DataAfterFiE
0
ns
tex
AeRPulseWidth
200
ns
tgr
STB PulseWidth
100
lps
Per.DataBeforeffi Hign
20
hx
tno
txo
twoe
Per.DataAtterSTEHigrr
50
ns
ns
ns
ffi:
OtoOutput
ffi
: 1 to OutputFloat
175
ns
250
ns
WF I: l to OE F : O
150
ns
tnog
A C K - : 0 t o O E |=F 1
150
ns
tsre
STEI:OtolBF:1
150
ns
tRra
RD:ltolBF:0
150
ns
hr
tsrt
FD-:Oto|NTR:0
200
ns
SFB=lto|NTR:1
150
ns
trur
ffi:ltolNTFt:1
150
ns
twr
WFI=Oto|NTR:0
200
tnes
Reset PulseWidth
ns
ns
20
500
Test
seenot€ 1
seenote2
}{OTE
1.|NTRT mayoccuras earlyas WFf .
2. Pulsewidthof initialREsetpulseaflerpoweron mustbe at l€est50 pSec.Subsoquent
Resetpulsesmaybe 500 ns
mrnrmum.
3-143
WAVEFORMS
INPUT)
MODE0 (BASTC
2312fi-22
MODEo (BASTC
OUTPUT)
231?56-23
3-1ll4
inbf
82CssA
WAVEFORMS(Continueo)
INPUT)
moDEI (STROBED
231256-24
MODEI (STROBED
OUTPUT)
fr
8'
ttt
rct
q.rlttt
231256-25
3-145
82C5sA
WAVEFORMS(Continued)
MODE2 (BTDfRECTTONAL)
OAIA FRO}I
t0a0 To al55
( T
'CEIIHEiAI
!us
o^la ?latr
3265lO rf hr|x:eat
DAtl
?titrxEnaL ?o t65
DAI
|:l6sron0
?31ffi-26
Nolc:
Anysequence
whereWF occursbeloreFffi ANDSTEoccursbeforeFD is permissible.
(INTR= IBFoFIASRTSTEoH-6
+ GF.FIASTffi(offi;
READ TII/|ING
WRITETIMING
?31255-2l,
231256-27
A.C.TESTINGINPUT,OUTPUTWAVEFORTI
A.C.TESTINGLOADCIRCUIT
br'
T
I
231256-29
ct.tlot
=
41256-30
'Vgg la Sei Al VariousVottlges DuringTastng To Gurantee
The Spocilicltion. C1 IncludesJig Capadtanc€.
A.C. T6ttrrg InputsAf€ Diven At 2.4V For A Logic I And 0..t5V
Fo A Logic 0 Timing Measurom€ntsfue Made At 2.0V Fot A
logic 1 And 0.8 For A Logic0.
3-146
APPENDIX I)
WARRANTY
D-l
D-2
LIMITED WARRANTY
andproducesto be free
RealTime Devices,Inc. warrantsthehardwareandsoftwareproductsit manufactures
from defectsin materialsandworkmanshipfor oneyeurfollowingthedateof shipmentfrom REAL TIME DEof productandis not transferable.
VICES.This warrantyis limited to theoriginalpurchaser
During theoneyearwiurantyperiod,REAL TIME DEVICESwill repairor replace,at its option,anydefective
productsor partsat no additionalcharge,providedthattheproductis returned,shippingprepaid,to REAL TIME
DEVICES.All replacedpartsandproductsbecomethepropertyof REAL TIME DEVICES.Before returning any
product for repair, customersare required to contactthe factory for an RMA number.
THIS LIMITED WARRANTY DOESNOT EXTEND TO ANY PRODUCTSWHICH HAVE BEEN DAMAGED AS A RESULTOF ACCIDENT,MISUSE,ABUSE (suchas:useof incorrectinput voltages,improperor
insufficientventilation,failureto follow theoperatinginstructionsthatareprovidedby REAL TIME DEVICES'
beyondthecontrolof REAL TIME DEVICES),OR AS A RESULTOF
"actsof God" or othercontingencies
SERVICEOR MODIFICATION BY ANYONE OTHERTHAN REAL TIME DEVICES.EXCEPTAS EXPRESSLYSETFORTHABOVE, NO OTHERWARRANTIESARE EXPRESSEDOR IMPLIED, INCLUDING,
BUT NOT LIMITED TO, ANY IMPLIED WARRANTIESOF MERCHANTABILITY AND FITNESSFOR A
PARTICULARPURPOSE,AND REAL TIME DEVICESEXPRESSLYDISCLAIMS ALL WARRANTIESNOT
STATED HEREIN. ALL IMPLIED WARRANTIES, INCLUDING IMPLIED WARRANTIES FOR
MECHANTABILITY AND FITNESSFORA PARTICULARPURPOSE,ARE LIMITED TO THE DURATION
OF THIS WARRANTY. IN THE EVENT THE PRODUCTIS NOT FREEFROM DEFECTSAS WARRANTED
ABOVE. THE PURCHASER'SSOLEREMEDY SHALL BE REPAIROR REPLACEMENTAS PROVIDED
ABOVE. LTNDERNO CIRCUMSTANCESWILL REAL TIME DEVICESBE LIABLE TO THE PURCHASER
OR ANY USERFOR ANY DAMAGES,INCLUDING ANY INCIDENTAL OR CONSEQUENTIALDAMAGES,EXPENSES,LOST PROFITS,LOST SAVINGS,OR OTHERDAMAGESARISING OUT OF THE USE
OR INABILITY TO USE THE PRODUCT.
SOME STATESDO NOT ALLOW THE EXCLUSIONOR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR CONSUMERPRODUCTS,AND SOMESTATESDO NOT ALLOW LIMITATIONS ON HOW LONG AN IMPLIED WARRANTY LASTS,SOTHE ABOVE LIMITATIONS OR EXCLU'
SIONSMAY NOT APPLY TO YOU.
THIS WARRANTY GIVES YOU SPECIFICLEGAL RIGHTS,AND YOU MAY ALSO HAVE OTHER
RIGHTSWHICH VARY FROM STATETO STATE.
D-3
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