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5.1.6 Create tests
Static faults and dynamic faults introduced above can be detected using logic test
and logic delay test respectively. Before these two tests, scan chain test (static) and scan
chain delay test (dynamic) should be conducted respectively. It is because the generation
of logic tests has pre-assumed the scan chain works precisely. And the stuck-at fault and
the transition fault along the scan chain and corresponding scan input pins of each scan
elements cannot be tested without applying scan tests.
5.1.7 Commit tests
Commit a test means saving the test data. When the test data is committed, it is
appended to the set of committed vectors. Once committed, the test data is isolated from
any further operation and other uncommitted test data.
5.1.8 Write vectors
After committing all required test vectors, they are ready to be written out and the
testbench is then generated. Common vector formats include Verilog, Standard Test
Interface Language (STIL), Waveform Generation Language (WGL), and Tester
Description Language (TDL).
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