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Step 1. Scan chain test generation.
Step 2. Test generation for the combinational feeder
and other scan elements except TLLs.
Step 3. Test generation for TLL cells.
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Figure 23. Test generation procedure for hybrid circuits.
Figure 23 shows the test generation flow. To begin with, the scan chain is tested. A
sequence of transitions of ones and zeros applied continuously in scan mode detects all
possible faults, along the scan chain, which include stuck-at faults, dynamic transition
faults, and the functional defect of the latch and test branch in the TLL cell. Typical static
sequence generated is repeating “00110011”. This tests all possible four cases, 0->0, 0->1,
1->1, and 1->0, for scan elements, in which the function of the latch in TLL cells is also
tested. And dynamic sequence, if any, is typically repeating “00111100”. As is known, the
worst case for a slow transition is when the initial state fully settled down. In all, correct
operation of the scan chain lays the foundation of all other following tests.
Second, assuming that the TLL cell is fault-free, generate tests for all
combinational logic blocks and other scan elements, where conventional ATPG
algorithms can be used. The fault-free TLL cell ensures exact fault propagation.
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