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is supposed to erase the history in the reset phase before every evaluation phase.
Remaining vectors in the truth table except the weak inputs are then applied statically
(static pattern). Secondly, dynamic patterns for all weak inputs are proposed to detect
structural transistor level faults analyzed in the TLL cell, with single fault assumption and
stuck-at faults, stuck-on faults, and stuck-open faults under consideration. Containing
those patterns, the functional test covers all testable structural faults inside the TLL.
Thirdly, with the scope of the whole hybrid netlist, the procedure of test generation is
proposed with three steps: scan chain test; test of feeders and other scan elements except
TLLs; functional pattern test of TLL cells. Implementation of this procedure is discussed
in the automatic test pattern generation (ATPG) chapter.
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