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Programming Model
Table 3-32. DSAT PRC Encoding
3
PRC
PCI Command
0010
IO Read
0110
Memory Read
1100
Memory Read Multiple
1110
Memory Read Line
Using an encoding other than the recommended value will result in
unpredictable DMA operation.
CRI: Cache-line Read Invalidate. If set, the DMA will use the
“Read-with-intent-to-modify” transfer type during PowerPC read
cycles. This will force processor cached data in the E and S states to
be invalidated during snoop hits. If cleared, the DMA will use the
“Read” transfer type. This will allow the processor to retain cached
data in the E and S states.
GBL: Global. If set, the DMA will assert the GBL_ pin during
PowerPC read cycles. This will allow the processor to snoop the DMA
transfer. If cleared, the GBL_ pin will not be asserted and the processor
will not be able to snoop the DMA transaction.
DMA Destination Address Register
Bit
XCSR + $268
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Offset
Name
DDAD
Operation
R/W
Reset
$00000000
Function
DMA
The DMA Destination Address Register (DDAD) contains the destination
address for a DMA transfer. If the destination is PCI space then this field
will represent a PCI address. If the destination is PowerPC space then this
field will represent a PowerPC address.
3-86
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