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I2C Interface
Sequential Read
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Note that the I C sequential read can be initiated by either an I2C
read (described here) or an I2C current address read. With an I2C
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read initiation, the first step in the programming sequence should be to test
the CMP bit for the operation-complete status. The next step is to initiate
a start sequence by first setting the STA and ENA bits in the I2COx
Register and then writing the device address (bits 24-30) and write bit (bit
31=0) to the I2TDx Register. The CMP bit will be automatically clear with
the write cycle to the I2TDx Register. The I2STx Register must now be
polled to test the CMP and ACKI bits. The CMP bit becomes set when the
device address and write bit have been transmitted, and the ACKI bit
provides status as to whether or not a slave device acknowledged the
device address. With the successful transmission of the device address, the
initial word address will be loaded into the I2TDx Register to be
transmitted to the slave device. Again, CMP and ACKI bits must be tested
for proper response. At this point, the slave device is still in a write mode.
Therefore, another start sequence must be sent to the slave to change the
mode to read by first setting the STA, ACKO, and ENA bits in the I2COx
Register and then writing the device address (bits 24-30) and read bit (bit
31=1) to the I2TDx Register. After CMP and ACKI bits have been tested
for proper response, the I2C master controller writes a dummy value
(data=don’t care) to the I2TDx Register.This causes the I2C master
controller to initiate a read transmission from the slave device. After the
I2C master controller has received a byte of data (indicated by DIN=1 in
the I2STx Register) and the CMP bit has also been tested for proper status,
the I2C master controller will respond with an acknowledge and the system
software may then read the data by polling the I2RDx Register. As long as
the slave device receives an acknowledge, it will continue to increment the
word address and serially clock out sequential data words. The I2C
sequential read operation is terminated when the I2C master controller
does not respond with an acknowledge. This can be accomplished by
setting only the ENA bit in the I2COx Register before receiving the last
data word. A stop sequence then must be transmitted to the slave device by
first setting the STP and ENA bits in the I2COx Register and then writing
a dummy data (data=don’t care) to the I2TDx Register. The I2STx
Register must now be polled to test CMP bit for the operation-complete
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