Download TSC693E Memory Controller / User`s Manual

TSC693E
3.9.4.
3.9.5.
3.10.
3.11.
3.12.
3.13.
3.14.
3.15.
3.16.
3.17.
3.18.
3.19.
3.19.1.
3.19.2.
3.19.3.
3.19.4.
3.19.5.
3.20.
3.21.
3.21.1.
3.21.2.
Fault Injection ....................................................................................... 31
Memory and I/O Parity ......................................................................... 31
Memory Redundancy .............................................................................. 32
Synchronous Traps .................................................................................. 32
Interrupts (Asynchronous Traps)............................................................. 33
General Purpose and Real Time Clock Timers ....................................... 36
Watch Dog............................................................................................... 38
UART ...................................................................................................... 40
Parity Checking ....................................................................................... 41
Error Handler........................................................................................... 42
System Availability ................................................................................. 47
Test mode and Test Access Port.............................................................. 47
EDAC Test............................................................................................ 47
Parity Test ............................................................................................. 47
Interrupt Test......................................................................................... 47
Error Test .............................................................................................. 48
Test Access Port (TAP) ........................................................................ 48
System Clock........................................................................................... 48
MEC Registers ........................................................................................ 49
Register Address Map........................................................................... 49
Register Configuration and Bit Allocation ........................................... 50
4.
4.1.
4.2.
4.2.1.
4.2.2.
4.2.3.
4.2.4.
4.2.5.
4.2.6.
MEMORY CONTROLLER SIGNAL DESCRIPTIONS ......................... 63
Memory Controller Signal Summary ...................................................... 63
MEC Detailed Signal Descriptions ......................................................... 65
IU/FPU Interface Signals ...................................................................... 65
Memory System Interface Signals ........................................................ 71
Interrupt and Control Signals................................................................ 75
Test Access Port Signals....................................................................... 77
UART Interface..................................................................................... 78
Power and Clock Signals ...................................................................... 79
5.
5.1.
5.1.1.
5.1.2.
5.1.3.
5.1.4.
5.2.
5.2.1.
5.2.2.
ELECTRICAL AND MECHANICAL SPECIFICATION........................ 80
Maximum Rating and DC Characteristics .............................................. 80
Maximum Ratings................................................................................. 80
Operating Range ................................................................................... 80
DC Characteristics over the Operating Range ...................................... 80
Capacitance Ratings.............................................................................. 81
Package Description ................................................................................ 81
Pin Assignments.................................................................................... 81
Package Diagram .................................................................................. 82
APPENDIX 1 - TIMING DIAGRAMS
MATRA MHS
Rev. D (10 Apr. 97)
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