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Direct memory access controller (DMA)
RM0031
Reset value: N/A
7
6
5
4
3
2
1
0
rw/r
rw/r
rw/r
rw/r
M1A[15:8]
r
r
r
rw/r
Bits 7:0 M1A[15:8]: Memory 1 address pointer (MSB)
The M1A pointer is the destination address when performing memory-to-memory transfers. Only bits
0, 1, 2, 3 and 4 are accessible. The other bits are fixed to allow a value range from 0x00 to 0x1F.
13.6.9
DMA channel 3 peripheral address low & memory 1 address low
register (DMA_C3PARL_C3M1ARL)
Address offset: Refer to Table 43: DMA register map on page 201
Reset value: 0x00
This register is write protected when the DMA channel is enabled (EN and GEN bits set)
and when the channel is busy (BUSY bit set).
This register has two different meanings depending on the MEM bit configuration:
•
Note:
DMA channel 3 peripheral address low (DMA_C3PARL)
This definition is valid when the MEM bit is reset.
7
6
5
4
3
2
1
0
rw/r
rw/r
rw/r
rw/r
PA[7:0]
rw/r
rw/r
rw/r
rw/r
Bits 7:0 PA[7:0]: Peripheral address pointer (LSB)
The PA Pointer is the source address if DIR = 0 or the destination address if DIR = 1.
•
Note:
DMA channel 3 memory 1 address low (DMA_C3M1ARL)
This definition is valid when the MEM bit is set.
7
6
5
4
3
2
1
0
rw/r
rw/r
rw/r
rw/r
M1A[7:0]
rw/r
rw/r
rw/r
rw/r
Bits 7:0 M1A[7:0]: Memory 1 address pointer (LSB)
The M1A pointer is the destination address when performing memory-to-memory transfers.
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