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µ PD42S4260, 424260
DC Characteristics
Parameter
Operating current
Standby
current
µ PD42S4260
(Recommended Operating Conditions unless otherwise noted)
Symbol
I CC1
I CC2
Test condition
RAS, CAS cycling
t RC = tRC (MIN.) , IO = 0 mA
MIN.
MAX.
Unit
Notes
t RAC = 60 ns
160
mA
1, 2, 3
t RAC = 70 ns
160
t RAC = 80 ns
145
RAS, CAS ≥ V IH (MIN.), I O = 0 mA
2
RAS, CAS ≥ V CC – 0.2 V, I O = 0 mA
µPD424260
RAS only refresh current
Operating current
(Fast page mode)
CAS before RAS
refresh current
CAS before RAS
I CC3
I CC4
I CC5
I CC6
long refresh current
(512 cycles / 128 ms,
only for the µ PD42S4260)
TYP.
0.15
RAS, CAS ≥ V IH (MIN.), I O = 0 mA
2
RAS, CAS ≥ V CC – 0.2 V, I O = 0 mA
1
RAS cycling, CAS ≥ VIH (MIN.)
t RC = tRC (MIN.) , IO = 0 mA
t RAC = 60 ns
160
t RAC = 70 ns
160
t RAC = 80 ns
145
t RAC = 60 ns
140
t RAC = 70 ns
140
t RAC = 80 ns
130
t RAC = 60 ns
160
t RAC = 70 ns
160
t RAC = 80 ns
145
CAS before RAS refresh:
t RC = 250.0 µs
RAS, CAS:
VCC – 0.2 V ≤ V IH ≤ V IH(MAX.)
0V ≤ V IL ≤ 0.2 V
t RAS ≤ 200 ns
Standby:
RAS, CAS ≥ V CC – 0.2 V
Address: VIH or VIL
WE, OE: VIH
I O = 0 mA
t RAS ≤ 1 µs
RAS ≤ VIL (MAX.), CAS cycling
t PC = tPC (MIN.), IO = 0 mA
RAS cycling
t RC = tRC (MIN.) , IO = 0 mA
mA
mA
1, 2, 3, 4
mA
1, 2, 5
mA
1, 2
200
µA
1, 2
300
µA
1, 2
150
µA
2
Self refresh current
(CAS before RAS self
refresh, only for the
µPD42S4260)
I CC7
RAS, CAS:
tRASS = 5 ms
VCC – 0.2 V ≤ VIH ≤ VIH (MAX.)
0 V ≤ VIL ≤ 0.2 V
I O = 0 mA
Input leakage current
I I(L)
VI = 0 to 5.5 V
All other pins not under test = 0 V
–10
+10
µA
Output leakage current
I O(L)
VO = 0 to 5.5 V
Output is disabled (Hi-Z)
–10
+10
µA
High level output voltage
VOH
I O = –2.5 mA
2.4
Low level output voltage
VOL
I O = +2.1 mA
V
0.4
V
Notes 1. ICC1 , ICC3 , ICC4 , ICC5 and ICC6 depend on cycle rates (tRC and tPC).
2. Specified values are obtained with outputs unloaded.
3. ICC1 and ICC3 are measured assuming that address can be changed once or less during RAS ≤
VIL (MAX.) and CAS ≥ V IH (MIN.).
4. ICC3 is measured assuming that all column address inputs are held at either high or low.
5. ICC4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.
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