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IRQ_POL_PIO40
IRQ_POL_PIO36
IRQ_POL_PIO35
0
0
0
0
External interrupt polarity for PIO[47]
External interrupt polarity for PIO[40]
External interrupt polarity for PIO[36]
External interrupt polarity for PIO[35]
0
0
Loadable Firmware | How To Use Loadable Firmware
DOC090903AN05EN | Revision 5 | English | 2015-01 | Released | Public
0
0
ADR_IN[15:12]
CS_COMP_SRC[19:12]
0
0
0
0
0
0
0
0
Chip Select compare value when internal
compare source is used
0
0 : internal (compare with CS_COM_VAL)
0
Logic level for Dual-Port memory address
lines [15:12] when used as input / output
pin (pio mode) or when the chip select
comparator is enabled
1
reserved
DIS_BUSY_TIMEOUT
Register
DPM_ARM_IF_CFG1 – DPM ARM Side Host Interface Configuration Register 0
0x0010 360c
Bits
31
30
29
28
27
26 25 24
3
23
reserved
0
This flag is not set, any access to the netX
host interface will be aborted after 256
system clocks
DATAOUT_VALID_TIME
IRQ_POL_PIO47
0
01 : 1 system clock
IRQ_POL_PIO72
Description
0
External interrupt polarity for PIO[72]
Value
WRITE_PROTECT
Name
This bit is set any following write accesses
to the register are impossible
Example HOST Interface Configuration
52/59
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
0 0 0 0 0 0
0
2
0
1
0
0
CS_COMP_VAL[19:12]
0
0x0100 0000
Table 10: netX50 DPM_ARM_IF_CFG1 Register
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