Download Alpha 21164 Microprocessor Hardware Reference Manual

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PM_MUX_SEL Register Fields . . . . . . . . . . . . . . . . . . . . . .
Bcache Configuration Register Fields . . . . . . . . . . . . . . . . . .
Bcache Tag Address Register Fields . . . . . . . . . . . . . . . . . . .
Loading and Locking Rules for External Interface
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EI_STAT Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . .
Syndromes for Single-Bit Errors . . . . . . . . . . . . . . . . . . . . .
Cbox IPR PALcode Restrictions . . . . . . . . . . . . . . . . . . . . . .
PALcode Restrictions Table . . . . . . . . . . . . . . . . . . . . . . . . .
PALcode Trap Entry Points . . . . . . . . . . . . . . . . . . . . . . . . .
Required PALcode Function Codes . . . . . . . . . . . . . . . . . . . .
Opcodes Reserved for PALcode . . . . . . . . . . . . . . . . . . . . . . .
HW_LD Format Description . . . . . . . . . . . . . . . . . . . . . . . .
HW_ST Format Description . . . . . . . . . . . . . . . . . . . . . . . . .
HW_REI Format Description . . . . . . . . . . . . . . . . . . . . . . . .
HW_MTPR and HW_MFPR Format Description . . . . . . . . .
Alpha 21164 Signal Pin Reset State . . . . . . . . . . . . . . . . . .
Internal Processor Register Reset State . . . . . . . . . . . . . . . .
Alpha 21164 Absolute Maximum Ratings . . . . . . . . . . . . . .
CMOS dc Input/Output Characteristics . . . . . . . . . . . . . . . .
Input Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bcache Loop Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . .
Alpha 21164 System Clock Output Timing (sysclk=Tø ) . . . .
Alpha 21164 Reference Clock Input Timing . . . . . . . . . . . .
ref_clk System Timing Stages . . . . . . . . . . . . . . . . . . . . . . .
Input Timing for sys_clk_out- or ref_clk_in-Based
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing for sys_clk_out- or ref_clk_in-Based
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bcache Control Signal Timing . . . . . . . . . . . . . . . . . . . . . . .
BiSt Timing for Some System Clock Ratios, Port
Mode=Normal (System Cycles) . . . . . . . . . . . . . . . . . . . . . .
BiSt Timing for Some System Clock Ratios, Port
Mode=Normal (CPU Cycles) . . . . . . . . . . . . . . . . . . . . . . . .
SROM Load Timing for Some System Clock Ratios (System
Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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