Download Alpha 21164 Microprocessor Hardware Reference Manual

5.1.25
Serial Line Transmit (SL_XMIT) Register . . . . . . . . . . . . . . .
5.1.26
Serial Line Receive (SL_RCV) Register . . . . . . . . . . . . . . . . .
5.1.27
Performance Counter (PMCTR) Register . . . . . . . . . . . . . . .
5.2
Memory Address Translation Unit (Mbox) IPRs . . . . . . . . . . . . . .
5.2.1
Dstream Translation Buffer Address Space Number
(DTB_ASN) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2
Dstream Translation Buffer Current Mode (DTB_CM)
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3
Dstream Translation Buffer Tag (DTB_TAG) Register . . . . .
5.2.4
Dstream Translation Buffer Page Table Entry (DTB_PTE)
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.5
Dstream Translation Buffer Page Table Entry Temporary
(DTB_PTE_TEMP) Register . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.6
Dstream Memory Management Fault Status (MM_STAT)
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.7
Faulting Virtual Address (VA) Register . . . . . . . . . . . . . . . . .
5.2.8
Formatted Virtual Address (VA_FORM) Register . . . . . . . . .
5.2.9
Mbox Virtual Page Table Base Register (MVPTBR) . . . . . . . .
5.2.10
Dcache Parity Error Status (DC_PERR_STAT) Register . . . .
5.2.11
Dstream Translation Buffer Invalidate All Process
(DTB_IAP) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.12
Dstream Translation Buffer Invalidate All (DTB_IA) Register
................................................
5.2.13
Dstream Translation Buffer Invalidate Single (DTB_IS)
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.14
Mbox Control Register (MCSR) . . . . . . . . . . . . . . . . . . . . . . .
5.2.15
Dcache Mode (DC_MODE) Register . . . . . . . . . . . . . . . . . . .
5.2.16
Miss Address File Mode (MAF_MODE) Register . . . . . . . . .
5.2.17
Dcache Flush (DC_FLUSH) Register . . . . . . . . . . . . . . . . . .
5.2.18
Alternate Mode (ALT_MODE) Register . . . . . . . . . . . . . . . . .
5.2.19
Cycle Counter (CC) Register . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.20
Cycle Counter Control (CC_CTL) Register . . . . . . . . . . . . . .
5.2.21
Dcache Test Tag Control (DC_TEST_CTL) Register . . . . . . .
5.2.22
Dcache Test Tag (DC_TEST_TAG) Register . . . . . . . . . . . . .
5.2.23
Dcache Test Tag Temporary (DC_TEST_TAG_TEMP)
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
External Interface Control (Cbox) IPRs . . . . . . . . . . . . . . . . . . . .
5.3.1
Scache Control (SC_CTL) Register (FF FFF0 00A8) . . . . . . .
5.3.2
Scache Status (SC_STAT) Register (FF FFF0 00E8) . . . . . . .
5.3.3
Scache Address (SC_ADDR) Register (FF FFF0 0188) . . . . . .
5.3.4
Bcache Control (BC_CONTROL) Register
(FF FFF0 0128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
5–31
5–32
5–33
5–38
5–38
5–39
5–40
5–41
5–43
5–44
5–46
5–47
5–49
5–50
5–52
5–52
5–53
5–54
5–56
5–58
5–60
5–60
5–61
5–62
5–63
5–64
5–66
5–68
5–69
5–72
5–75
5–78