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Chapter 5: Specifying Timing Constraints in Synplify
attribute syn_black_box : boolean ;
attribute syn_black_box of bbram : entity is true ;
attribute syn_isclock : boolean;
attribute syn_isclock of clk: signal is true;
attribute syn_gatedclk_clock_en : string;
attribute syn_gatedclk_clock_en of clk : signal is "en";
end entity bbram;
architecture bb of bbram is
attribute syn_force_seq_prim : boolean;
attribute syn_force_seq_prim of bb : architecture is true;
begin
end architecture bb;
syn_gatedclk_clock _en
The syn_gatedclk_clock_en directive specifies the enable pin to be used in fixing the
gated clocks. To use the syn_gatedclk_clock_en directive with a black box, you must
also identify the clock signal with the syn_isclock directive and indicate that the fix
gated clocks algorithm can be applied with the syn_force_seq_prim directive. The
data type is String.
syn_gatedclk_clock _en Verilog Syntax
object /* synthesis syn_gatedclk_clock_en = "value" */ ;
where
•
object is the module name
•
value is the name of the enable pin
syn_gatedclk_clock _en Verilog Syntax Example
module bbe (ena, clk, data_in, data_out)
/* synthesis syn_black_box */
/* synthesis syn_force_seq_prim=1 */;
input clk
/* synthesis syn_isclock = 1 */
/* synthesis syn_gatedclk_clock_en="ena" */;
input data_in,ena;
output data_out;
endmodule
syn_gatedclk_clock _en VHDL Syntax
attribute syn_gatedclk_clock_en of object: objectType is value ;
where
•
object is the entity name of the black box
syn_gatedclk_clock _en VHDL Syntax Example
architecture top of top is component bbram
port (myclk : in bit;
opcode : in bit_vector(2 downto 0);
a, b : in bit_vector(7 downto 0);
rambus : out bit_vector(7 downto 0) );
end component;
attribute syn_black_box : boolean;
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Timing Constraints User Guide
UG612 (v 11.1.1) April 29, 2009