Download FIFO Generator Core v3.3 User Guide

Schedule of Figures
Chapter 2: Core Overview
Figure 2-1: FIFO with Independent Clocks: Interface Signals . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 3: Generating the Core
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 3-4:
Figure 3-5:
Figure 3-6:
Main FIFO Generator Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Options and Data Port Parameters Screen . . . . . . . . . . . . . . . . .
Optional Flags, Handshaking, and Initialization Options Screen. . . . . . . . .
Programmable Flags Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Count and Reset Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
31
33
35
36
37
Chapter 4: Designing with the Core
Figure 4-1: FIFO with Independent Clocks: Write and Read Clock Domains . . . . . . . . .
Figure 4-2: Functional Implementation of a FIFO with Independent Clock Domains .
Figure 4-3: Functional Implementation of Built-in FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-4: Functional Implementation of a Common Clock FIFO using
Block RAM or Distributed RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-5: Functional Implementation of a Common Clock FIFO using
Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-6: Write Operation for a FIFO with Independent Clocks. . . . . . . . . . . . . . . . . . .
Figure 4-7: Standard Read Operation for a FIFO with Independent Clocks . . . . . . . . . .
Figure 4-8: FWFT Read Operation for a FIFO with Independent Clocks . . . . . . . . . . . . .
Figure 4-9: Write and Read Operation for a FIFO with Common Clocks . . . . . . . . . . . . .
Figure 4-10: Handshaking Signals for a FIFO with Independent Clocks . . . . . . . . . . . . .
Figure 4-11: Handshaking Signals for a FIFO with Common Clocks . . . . . . . . . . . . . . . .
Figure 4-12: Programmable Full Single Threshold: Threshold Set to 7. . . . . . . . . . . . . . .
Figure 4-13: Programmable Full with Assert and Negate Thresholds:
Assert Set to 10 and Negate Set to 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-14: Programmable Empty with Single Threshold: Threshold Set to 4 . . . . . . .
Figure 4-15: Programmable Empty with Assert and Negate Thresholds:
Assert Set to 7 and Negate Set to 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-16: Write and Read Data Counts for FIFO with Independent Clocks . . . . . . . .
Figure 4-17: 1:4 Aspect Ratio: Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-18: 1:4 Aspect Ratio: Status Flag Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-19: 4:1 Aspect Ratio: Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-20: 4:1 Aspect Ratio: Status Flag Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-21: SBITERR and DBITERR Outputs in the FIFO Generator Core . . . . . . . . . .
Figure 4-22: Synchronous Reset: FIFO with Independent Clock . . . . . . . . . . . . . . . . . . . .
Figure 4-23: Asynchronous Reset: FIFO with Common Clock . . . . . . . . . . . . . . . . . . . . . .
Figure 4-24: Synchronous Reset: FIFO with a Common Clock . . . . . . . . . . . . . . . . . . . . . .
FIFO Generator v3.3 User Guide
UG175 April 2, 2007
www.xilinx.com
40
41
43
44
45
46
48
48
49
50
51
53
53
54
55
57
58
59
59
60
61
62
62
63
7