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Chapter 4: IP Core Architecture
PCI Express Avalon-MM Bridge
4–23
specifies 32-bit or 64-bit PCI Express addressing for the translated address. Refer to
Figure 4–12 on page 4–24. The most significant bits of the Avalon-MM address are
used by the system interconnect fabric to select the slave port and are not available to
the slave. The next most significant bits of the Avalon-MM address index the address
translation entry to be used for the translation process of MSB replacement.
For example, if the core is configured with an address translation table with the
following attributes:
■
Number of Address Pages—16
■
Size of Address Pages—1 MByte
■
PCI Express Address Size—64 bits
then the values in Figure 4–12 are:
■
N = 20 (due to the 1 MByte page size)
■
Q = 16 (number of pages)
■
M = 24 (20 + 4 bit page selection)
■
P = 64
In this case, the Avalon address is interpreted as follows:
■
Bits [31:24] select the TX slave module port from among other slaves connected to
the same master by the system interconnect fabric. The decode is based on the base
addresses assigned in Qsys.
■
Bits [23:20] select the address translation table entry.
■
Bits [63:20] of the address translation table entry become PCI Express address bits
[63:20].
■
Bits [19:0] are passed through and become PCI Express address bits [19:0].
The address translation table can be hardwired or dynamically configured at run
time. When the IP core is parameterized for dynamic address translation, the address
translation table is implemented in memory and can be accessed through the CRA
slave module. This access mode is useful in a typical PCI Express system where
address allocation occurs after BIOS initialization.
For more information about how to access the dynamic address translation table
through the control register access slave, refer to the “Avalon-MM-to-PCI Express
Address Translation Table” on page 6–9.
August 2014
Altera Corporation
IP Compiler for PCI Express User Guide