Download Xilinx UG190 Virtex

R
Specific Guidelines for I/O Supported Standards
HSTL Class III (1.8V)
Figure 6-61 shows a sample circuit illustrating a valid termination technique for HSTL
Class III (1.8V).
External Termination
VTT = 1.8V
IOB
HSTL_III_18
IOB
HSTL_III_18
RP = Z0 = 50Ω
+
Z0
–
VREF = 1.1V
DCI
IOB
IOB
VCCO = 1.8V
RVRP = Z0= 50Ω
HSTL_III_DCI_18
HSTL_III_DCI_18
+
Z0
VREF = 1.1V
–
ug190_6_59_030306
Figure 6-61:
HSTL Class III (1.8V) Termination
Table 6-25 lists the HSTL Class III (1.8V) DC voltage specifications.
Table 6-25:
HSTL Class III (1.8V) DC Voltage Specifications
Min
Typ
Max
1.7
1.8
1.9
VREF (2)
–
1.1
–
VTT
–
VCCO
–
VIH
VREF + 0.1
–
–
VIL
–
–
VREF – 0.1
VOH
VCCO – 0.4
–
–
VOL
–
–
0.4
IOH at VOH (mA)(1)
–8
–
–
IOL at VOL (mA)(1)
24
–
–
VCCO
Notes:
1. VOL and VOH for lower drive currents are sample tested.
2. Per EIA/JESD8-6, “The value of VREF is to be selected by the user to provide optimum noise margin in
the use conditions specified by the user.”
Virtex-5 FPGA User Guide
UG190 (v4.4) December 2, 2008
www.xilinx.com
267