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Download Xilinx UG190 Virtex
Transcript
R Chapter 2: Clock Management Technology Clock Switching Between Two DCMs Figure 2-13 illustrates switching between two clocks from two DCMs while keeping both DCMs locked. IBUFG DCM_ADV CLKIN CLKA CLKFB RST PSINCDEC PSEN PSCLK DADDR[6:0] DI[15:0] DWE DEN DCLK IBUFG CLKFB RST PSINCDEC PSEN PSCLK DADDR[6:0] DI[15:0] DWE DEN DCLK BUFGMUX I0 LOCKED DO(15:0) DCM_ADV CLKIN CLKB CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 BUFG I0 S BUFG CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED DO(15:0) ug190_2_14_032506 Figure 2-13: 76 Clock Switching Between Two DCMs www.xilinx.com Virtex-5 FPGA User Guide UG190 (v4.4) December 2, 2008
