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Download Cypress Semiconductor FX2LP Technical information
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OED Port D Output Enable SFR 0xB5 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 OEE Port E Output Enable SFR 0xB6 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 The bits in 0EA - 0EE turn on the output buffers for the five IO Ports PORTA-PORTE. Setting a bit to 1 turns on the output buffer, setting it to 0 turns the buffer off. EP01STAT Endpoint 0 and 1 Status SFR 0xBA b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 EP1INBSY EP1OUTBSY EP0BSY R R R R R R R R 0 0 0 0 0 0 0 0 GPIFTRIG Endpoint 2,4,6,8 GPIF Slave FIFO Trigger see Section 15.14 SFR 0xBB b7 b6 b5 b4 b3 b2 b1 b0 DONE 0 0 0 0 R/W EP1 EP0 R/W R R R R R/W R/W R/W 1 0 0 0 0 x x x Chapter 15. Registers Page 15-11
