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Timing Analyzer Reports
6192 Report
Since the cnt4 design does not use a 6000 family device, the report shown is for a
different design. It is an example of a design.mpt file.
Module Timing Report
-------------------Design Name: m_sh01_1
Part Name: ispLSI6192SM-70LM208
This report contains the internal timing characteristics
and the path delays starting or ending at any module I/O
Module Information
Primitive Name: RGTRS07
Instance Name: REG_1
Functional Description: Register/Counter
Timing Description
Max/Min in ns
1.External Timing:
-----------------16-bit Timer
Clock to Carry Out/TC (16-bit)
2.Internal Timing:
-----------------Clock to Carry Out/TC (16-bit)
Carry In/Count Hold Setup to Clock
Carry In/Count Hold Hold to Clock
Carry In/Count Hold to Carry Out/TC
Preload Setup to Clock
Preload Hold to Clock
Preset Setup to Clock
Preset Hold to Clock
Select to Parallel Data Out
Select Setup to Clock
Select Hold to Clock
Enable Setup to Clock
Enable Hold from Clock
Reset to Data Out
Reset Pulse Duration
3.Path Timing:
---------------Delay Added for Reg./Counter Out to MIO
Delay Added for Reg./Counter Out to GRP
Delay Added for MIO to Reg./Counter
Delay Added for GRP to Reg./Counter
125.00
18.00
18.00
7.60
0.00
0.00
7.60
0.00
7.60
0.00
14.60
7.60
0.00
7.60
0.00
12.00
12.00
1.00
1.00
4.00
4.00
Primitive Name: RAM2S07
Instance Name: RAM_0
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