Download MPC7400 RISC Microprocessor User`s Manual

Freescale Semiconductor, Inc.
CONTENTS
Freescale Semiconductor, Inc...
Paragraph
Number
3.7.3.7
3.7.3.8
3.7.3.8.1
3.7.3.8.2
3.7.3.9
3.7.3.10
3.7.4
3.7.5
3.7.5.1
3.7.5.2
3.7.5.3
3.7.6
3.7.7
3.7.7.1
3.7.7.2
3.7.7.3
3.7.8
3.7.8.1
3.7.8.2
3.7.8.3
3.8
3.9
3.9.1
3.9.2
3.9.3
Title
Page
Number
L2 Cache Global Invalidation...................................................................
L2 Cache Flushing....................................................................................
L2 Cache Hardware Flush ....................................................................
L2 Cache Software Flush .....................................................................
L2 Cache Clock and Timing Controls ......................................................
L2 Cache Power Management and Test Controls ....................................
L2 Cache Initialization..................................................................................
L2 Cache Operation ......................................................................................
L2 Cache Allocation on Cache Misses .....................................................
L2 Cache Replacement Selection .............................................................
Store Hit to a Shared or Recent L2 Cache Block .....................................
L2 Cache Clock Configuration .....................................................................
L2 Cache Testing ..........................................................................................
Testing Overall L2 Cache Operation ........................................................
Testing L2 Cache External SRAMs .........................................................
Testing L2 Cache Tags .............................................................................
L2 Cache SRAM Timing Examples .............................................................
Pipelined Burst SRAM .............................................................................
Late-Write SRAM ....................................................................................
PB3 SRAM ...............................................................................................
System Bus Interface Unit ................................................................................
MPC7400 Caches and System Bus Transactions .............................................
Bus Operations Caused by Cache Control Instructions................................
Transfer Attributes........................................................................................
Snooping .......................................................................................................
3-57
3-58
3-58
3-59
3-60
3-61
3-61
3-62
3-64
3-64
3-65
3-65
3-65
3-66
3-66
3-66
3-67
3-68
3-69
3-70
3-72
3-72
3-73
3-74
3-76
Chapter 4
Exceptions
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.5
4.6
4.6.1
4.6.2
4.6.2.1
MPC7400 Microprocessor Exceptions ............................................................... 4-3
Exception Recognition and Priorities ................................................................. 4-5
Exception Processing .......................................................................................... 4-8
Enabling and Disabling Exceptions.............................................................. 4-11
Steps for Exception Processing..................................................................... 4-12
Setting MSR[RI] ........................................................................................... 4-12
Returning from an Exception Handler.......................................................... 4-13
Process Switching ............................................................................................. 4-13
Data Stream Prefetching and Exceptions.......................................................... 4-14
Exception Definitions ....................................................................................... 4-14
System Reset Exception (0x00100).............................................................. 4-15
Machine Check Exception (0x00200) .......................................................... 4-16
Machine Check Exception Enabled (MSR[ME] = 1)............................... 4-18
Contents
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