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Exception Processing
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The ßoating-point unavailable exception can be masked by setting MSR[FP].
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The AltiVec unavailable exception can be masked by setting MSR[VEC].
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IEEE ßoating-point enabled exceptions (a type of program exception) are ignored
when both MSR[FE0] and MSR[FE1] are cleared. If either bit is set, all IEEE
enabled ßoating-point exceptions are taken and cause a program exception.
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The trace exception is enabled by setting either MSR[SE] or MSR[BE].
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4.3.2 Steps for Exception Processing
After it is determined that the exception can be taken (all instruction-caused exceptions
occurring earlier in the instruction stream have been handled, the instruction that caused the
exception is next to be retired, and by conÞrming that the exception is enabled for the
exception condition), the processor does the following:
1. SRR0 is loaded with an instruction address that depends on the type of exception.
See the individual exception description for details about how this register is used
for speciÞc exceptions.
2. SRR1[0, 7Ð9] are cleared;
SRR1[1Ð5, 10Ð15] are loaded with information speciÞc to the exception type;
and SRR1[6, 16Ð31] are loaded with a copy of the corresponding MSR bits.
3. The MSR is set as described in Table 4-4. The new values take effect as the Þrst
instruction of the exception-handler routine is fetched.
Note that MSR[IR] and MSR[DR] are cleared for all exception types; therefore,
address translation is disabled for both instruction fetches and data accesses
beginning with the Þrst instruction of the exception-handler routine.
4. Instruction fetch and execution resumes, using the new MSR value, at a location
speciÞc to the exception type. The location is determined by adding the exception's
vector (see Table 4-2) to the base address determined by MSR[IP]. If IP is cleared,
exceptions are vectored to the physical address 0x000n_nnnn. If IP is set, exceptions
are vectored to the physical address 0xFFFn_nnnn. For a machine check exception
that occurs when MSR[ME] = 0 (machine check exceptions are disabled), the
checkstop state is entered (the machine stops executing instructions). See
Section 4.6.2, ÒMachine Check Exception (0x00200).Ó
4.3.3 Setting MSR[RI]
An operating system may handle MSR[RI] as follows:
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4-12
In the machine check and system reset exceptionsÑIf MSR[RI] is cleared, the
exception is not recoverable. If it is set, the exception is recoverable with respect to
the processor.
MPC7400 RISC Microprocessor UserÕs Manual
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