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Execution Unit Timings
6.4.4 Effect of Floating-Point Exceptions on Performance
For the highest and most predictable ßoating-point performance, all exceptions should be
disabled in the FPSCR and MSR and FPSCR[NI] should be set.
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If any exceptions are enabled (through a combination of MSR[FE] and one or more of the
FPSCR enable bits), the MPC7400 FPU takes one addition cycle to complete instructions.
This does not affect latency for data dependency. It may however, degrade performance by
consuming limited CQ resources for 1 extra cycle per instruction.
6.4.5 Load/Store Unit Execution Timing
In addition to executing the PowerPC load and store instructions, the LSU also executes the
AltiVec LRU and transient instructions. The execution of most load and store instructions
is pipelined. The LSU has two pipeline stages. The Þrst is for effective address calculation
and MMU translation and the second is for accessing data in the cache. Load and store
instructions have a two-cycle latency and one-cycle throughput.
If operands are misaligned, additional latency may be required either for an alignment
exception to be taken or for additional bus accesses. Load instructions that miss in the cache
block subsequent cache accesses during the cache line reÞll. Table 6-8 gives load and store
instruction execution latencies.
6.4.5.1 Effect of Operand Placement on Performance
The PowerPC VEA states that the placement (location and alignment) of operands in
memory may affect the relative performance of memory accesses, and in some cases affect
it signiÞcantly. The effects memory operand placement has on performance are shown in
Table 6-1.
The best performance is guaranteed if memory operands are aligned on natural boundaries.
For the best performance across the widest range of implementations, the programmer
should assume the performance model described in Chapter 3, ÒOperand Conventions,Ó in
The Programming Environments Manual.
The effect of misalignment on memory access latency is the same for big- and little-endian
addressing modes except for multiple and string operations that cause an alignment
exception in little-endian mode.
In Table 6-1, optimal means that one effective address (EA) calculation occurs during the
memory operation. Good means that multiple EA calculations occur during the operation,
which may cause additional bus activities with multiple bus transfers. Poor means that an
alignment exception is generated.
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MPC7400 RISC Microprocessor UserÕs Manual
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