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Timing Considerations
6.3 Timing Considerations
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The MPC7400 is a superscalar processor; as many as three instructions can be issued to the
execution units (one branch instruction to the BPU, and two instructions issued from the IQ
to the other execution units) during each clock cycle. Only one instruction can be
dispatched to each execution unit.
Although instructions appear to the programmer to execute in program order, the MPC7400
improves performance by executing multiple instructions at a time, using hardware to
manage dependencies. When an instruction is dispatched, the register Þle provides the
source data to the execution unit. The register Þles and rename register have sufÞcient
bandwidth to allow dispatch of two instructions per clock under most conditions.
The MPC7400Õs BPU decodes and executes branches immediately after they are fetched.
When a conditional branch cannot be resolved due to a CR data dependency, the branch
direction is predicted and execution continues from the predicted path. If the prediction is
incorrect, the following steps are taken:
1.
2.
3.
4.
The instruction queue is purged and fetching continues from the correct path.
Any instructions ahead of the predicted branch in the CQ are allowed to complete.
Instructions after the mispredicted branch are purged.
Dispatching resumes from the correct path.
After an execution unit Þnishes executing an instruction, it places resulting data into the
appropriate GPR, FPR, or VR rename register. The results are then stored into the correct
GPR, FPR, or VR during the write-back stage. If a subsequent instruction needs the result
as a source operand, it is made available simultaneously to the appropriate execution unit,
which allows a data-dependent instruction to be decoded and dispatched without waiting to
read the data from the register Þle. Branch instructions that update either the LR or CTR
write back their results in a similar fashion.
The following section describes this process in greater detail.
6.3.1 General Instruction Flow
As many as four instructions can be fetched into the instruction queue (IQ) in a single clock
cycle. Instructions are issued to the various execution units from the IQ. The MPC7400 tries
to keep the IQ full at all times, unless instruction cache throttling is operating.
The number of instructions requested in a clock cycle is determined by the number of
vacant spaces in the IQ during the previous clock cycle. This is shown in the examples in
this chapter. Although the instruction queue can accept as many as four new instructions in
a single clock cycle, if only one IQ entry is vacant, only one instruction is fetched. Typically
instructions are fetched from the on-chip instruction cache, but they may also be fetched
from the branch target instruction cache (BTIC). If the instruction request hits in the BTIC,
it can usually present the Þrst two instructions of the new instruction stream in the next
Chapter 6. Instruction Timing
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