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Chapter 13
Fleet
In this section we present the design and operation of a novel computer architecture we have been
developing, called Fleet, along with the development of a simulator for it, developed in the RAMP
Description Language (RDL). This is intended as a
walk-through for a designer wishing to experiment
with Fleet, and includes an architectural description (see Section 13.1), a guide to the code (see
Section 13) and instructions for building and programming a Fleet. Not only is Fleet a novel architecture, but this work represents the first hardware
implementation of a complete Fleet processor capable of executing code, though there have been
circuit-test ASICs with the name Fleet.
It is interesting to note that while this project has
successfully made good use of RDL it is not part of
the main RAMP effort. Though it is obviously a
hardware projects with some element of computer
architecture, there is quite a bit of variety when
compared to the manycore experiments which are
the bastion of RAMP. This shows some of the main
strength of RDL, though clearly rooted in the needs
of RAMP, it has proven useful on a slightly wider
range of applications.
to guarantee sequential operation of seas of transistors, only to realize now that we want concurrent processors in the end and that sequentiality is
costly and counter productive.
13.1.1
ISA
A classic ISA is focused on the storage (register
file or memory) and operation (ALU, etc.) operations relying on the hardware designer to be clever
about making these things happen. This was a reasonable approach as it allows an assembly language
programmer to easily translate an algorithm, and a
hardware designer to optimize these expensive transistor heavy operations.
Fleet is based around collections of concurrent
instances of a single instruction: move. The ISA
thus focuses on the movement of data, the expensive operation given the relative cost of transistors
and wires, allowing the high performance hardware
designer and programmer to cooperate rather than
working against one another. Of course storage,
computation and sequentiality are still necessary,
but these operations in Fleet are encoded in the
locations to which data items are moved and dependencies between moves.
13.1 A New Architecture
In many ways Fleet turns the job of microarchitectural scheduling over to the compiler or proFleet [31, 85, 86, 87] is a novel computer architecgrammer rather than forcing a architect or hardture based on the idea that the ISA should be foware designer to make the relevant decisions. In
cused on exposing the hardware’s abilities to the
essence one might view a Fleet processor as a
programmer, instead of hiding them below abstracstandard Tomasulo or Out-of-Order processor core,
tions. Most notably, in the years since the emerfrom which the forwarding logic, score-boarding
gence of class CISC and RISC architectures, there
and such logic have been removed. This shift means
has been a cost inversion in IC design between wires
that a Fleet processor can easily be more efficient,
and transistors. Transistors, once the most expenparticularly for streaming applications, at the cost
sive part of a CMOS IC, are now often considered
of a more advanced compiler or a better assembly
free as they fit easily below the massive amounts of
language programmer.
on chip wires necessary to implement busses and
Figure 54 shows a high level hypothetical block
other higher performance interconnects. Taking
diagram of a Fleet processor. A Fleet procesthis a step further, we have worked for 30 years
sor consits of a collection of operators over data
0 The ideas behind Fleet are in main the work of Ivan
words called Ships1 , and some form of switch fabSutherland, and numerous others including Adam Megacz
and Igor Benko.
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1 If
you don’t like nautical themed jokes, we recommend