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Program 32 FIFO.rdl
unit < Type , Depth , MemType , AWidth > {
opaque input $Type Input ;
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opaque output $Type Output ;
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plugin Verilog $MemType < $AWidth , " Input " , "" > Memory ;
plugin Verilog " FIFO " < $Depth , $AWidth > FIFO ;
plugin Verilog " FIFOUnit " <" FIFO " , " Memory " , " Input " , " Output " > FIFOUnit ;
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plugin ::1:: Platforms :: ModelSim " SetParam " < $MemType , " ModelSimMemory " >
SetMemModelSim ;
plugin ::1:: Platforms :: XUP " SetParam " < $MemType , " Virtex2ProMemory " > SetMemXUP
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;
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plugin ::1:: Platforms :: S3 " SetParam " < $MemType , " Spartan3Memory " > SetMemS3 ;
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plugin ::1:: Platforms :: CaLinx2 " SetParam " < $MemType , " VirtexEMemory " >
SetMemCaLinx2 ;
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plugin " SetParam " < $MemType , " Dummy " > SetNoMemory ;
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consisting of its count value after the appropriate 7.4.1 Unit: CounterExample
action is taken upon receipt of each input message.
Of course if it receives no input, it will produce no This is the top level unit of the design, as may be
output. This can be summed up in a simple state noted by its lack of input and output ports. This
unit instantiates the other three and connects them
transition diagram such as in Figure 25.
together as shown in Figure 24.
While this is a simple example, and smaller than
In addition to the examples of unit instantiations
a typical unit (particularly for an RDF design),
shown in the code for this module, you are enit illustrates the basics of RDL. The ::Counter is
couraged to examine both the channel declarations
declared to accept unstructured 1-bit messages at
and, more interestingly, the port-channel connecits port “UpDown” (::Counter.UpDown) and protions. There are three ways to connect a port to
duce 32-bit messages at its output port “Count”
a channel and all of them have been shown in this
(::Counter.Count). Of course this is a leaf unit,
unit.
which will be implemented directly in the host lanIn addition to the two commonly used in Verguage (Verilog or Java for example).
ilog (named and positional), the third and most
RDL and the compiler also support hierarchi- interesting is on line 11: Channel OutChannel { ->
cally defined units like CounterExample in this code DisplayNumX.Value };, which is a channel with a
snippet. Inside this unit, there are two channels, single connection. The source of this channel is
shown without detailed timing models, which are connected elsewhere, but here the destination conused to connect the three unit instances. This ex- nection is specified as the input port Value on the
ample also shows all three styles of port connections unit instance named DisplayNumX. This method of
named (line 3), positional (line 5) and explicit (line connections, while slightly more verbose than the
11). Explicit connections can use qualified dynamic other two allows a connection to be made at a high
identifiers to specify connection of a local channel level of the instance hierarchy, without declaring
to a port significantly lower in the hierarchy, with- and connecting channels at each intermediate level.
out explicit pass-through connections at each level This is particularly useful for debugging.
making debugging and modification for test much
In addition to the port, channel and unit ineasier.
stances, there are several plugin invocations in ProThis section includes a brief description of each gram 33. A plugin invocation starts with the keyof the units in the counter example. Shown word plugin, followed by a string literal specifying
in Figure 24 is a diagram of the overall struc- the plugin to run, and finally an name for this pluture of the counter example system. Please note gin invocation. Note that plugins may also accept
that the counter example source code can be parameters, and be limited to run only for specific
downloaded from the RAMP website [9] in the platforms or platforms which generate code in speexamples/counterexample directory inside of the cific languages.
RDLC2 distribution zipfile.
As an example here is one of the plugin invo52