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Chapter 13
Simulating With Code Coverage
Introduction
ModelSim Code Coverage gives you graphical and report file feedback on which executable
statements, branches, conditions, and expressions in your source code have been executed. It
also measures bits of logic that have been toggled during execution.
Note
The functionality described in this lesson requires a coverage license feature in your
ModelSim license file. Please contact your Mentor Graphics sales representative if you
currently do not have such a feature.
Design Files for this Lesson
The sample design for this lesson consists of a finite state machine which controls a behavioral
memory. The test bench test_sm provides stimulus.
The ModelSim installation comes with Verilog and VHDL versions of this design. The files are
located in the following directories:
Verilog – <install_dir>/examples/tutorials/verilog/coverage
VHDL – <install_dir>/examples/tutorials/vhdl/coverage
This lesson uses the Verilog version in the examples. If you have a VHDL license, use the
VHDL version instead. When necessary, we distinguish between the Verilog and VHDL
versions of the design.
Related Reading
User’s Manual Chapter: Code Coverage.
Compile the Design
Enabling Code Coverage is a simple process: You compile the design files and identify which
coverage statistics you want to collect. Then you load the design and tell ModelSim to produce
those statistics.
1. Create a new directory and copy the tutorial files into it.
ModelSim SE Tutorial, v10.1
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