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Download A13 User Manual V1.30 - linux
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TP_INT_FIFOC 0x10 TP Interrupt FIFO Control Register TP_INT_FIFOS 0x14 TP Interrupt FIFO Status Register TP_CDAT 0x1C TP Common Data Register TP_DATA 0x24 TP Data Register TP_IO_CONFIG 0x28 TP PORT IO Configure Register TP_PORT_DATA 0x2C TP Port Data Register 25.6. TP Register Description 25.6.1. TP Control Register 0 Offset: 0x00 Bit Read/ Write Register Name: TP_CTRL Default /Hex Description ADC_FIRST_DLY. ADC First Convert Delay setting Based on ADC First Convert Delay Mode select 31:24 R/W 0xF 23 R/W 0x1 ADC_FIRST_DLY_MODE. ADC First Convert Delay Mode Select 0: CLK_IN/16 1: CLK_IN/16*256 22 R/W 0x0 ADC_CLK_SELECT. ADC Clock Source Select: 0: HOSC(24MHZ) 1: Audio PLL 21:20 R/W 0x0 ADC_CLK_DIVIDER. ADC Clock Divider(CLK_IN) 00: CLK/2 01: CLK/3 10: CLK/6 11: CLK/1 In TP mode, these two bits must set 1x 19:16 R/W 0x0 FS_DIV. ADC Sample Frequency Divider 0000: CLK_IN/2(20-n) 0001: CLK_IN/2(20-n) 0010: CLK_IN/2(20-n) …. 1111: CLK_IN/32 15 :0 R/W 0x0 T_ACQ. Touch panel ADC acquire time CLK_IN/(16*N) A13 User Manual V1.3 Copyright © 2013 Allwinner Technology. All Rights Reserved. 260
