Download A13 User Manual V1.30 - linux

This special clock = Clock Source/Divider N/Divider M.
30:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL6
10: PLL5
11: /
23:18
/
/
/
17:16
R/W
0x0
CLK_DIV_RATIO_N.
Clock pre-divide ratio (n)
The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.
15:4
/
/
/
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.
3:0
R/W
6.4.24.
SD2 Clock (Default: 0x00000000)
Offset: 0x90
Bit
Read/W
rite
Register Name: SD2_SCLK_CFG_REG
Default/
Hex
Description
31
R/W
0x0
SCLK_GATING.
Gating Special Clock(Max Clock = 200MHz)
0: Clock is OFF
1: Clock is ON
This special clock = Clock Source/Divider N/Divider M.
30:26
/
/
/
25:24
R/W
0x0
CLK_SRC_SEL.
Clock Source Select
00: OSC24M
01: PLL6
10: PLL5
11: /.
23:18
/
/
/
17:16
R/W
0x0
CLK_DIV_RATIO_N.
Clock pre-divide ratio (n)
The select clock source is pre-divided by 2^n. The divider is 1/2/4/8.
15:4
/
/
/
0x0
CLK_DIV_RATIO_M.
Clock divide ratio (m)
The pre-divided clock is divided by (m+1). The divider is from 1 to 16.
3:0
6.4.25.
R/W
SS Clock (Default: 0x00000000)
Offset: 0x9C
A13 User Manual V1.3
Register Name: SS_SCLK_CFG_REG
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