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automatically.
Set 0 to the bit will stop the corresponding DMA channel and reset its
state machine.
30
R
0x0
DDMA_BSY_STA.
DMA Busy Status.
0: DMA idle
1: DMA busy.
29
R/W
0x0
DDMA_CONTI_MODE_EN.
DMA Continuous Mode Enable.
0: Disable, 1: Enable.
28
/
/
/
27
/
/
/
0x0
DDMA_DST_DATA_WIDTH.
DMA Destination Data Width.
00: 8-bit
01: 16-bit
10: 32-bit
11: /
0x0
DDMA_DST_BST_LEN.
DMA Destination Burst Length.
00: 1,
01: 4.
10: 8
11: /
0x0
DDMA_ADDR_MODE.
DMA Destination Address Mode
DMA Source Address Mode
0x0: Linear Mode
0x1: IO Mode
0x2: Horizontal Page Mode
0x3: Vertical Page Mode
0x0
DDMA_DST_DRQ_SEL.
Dedicated DMA Destination DRQ Type
0x0: SRAM memory
0x1: SDRAM memory
0x2: /
0x3: NAND Flash Controller (NFC)
0x4: USB0
0x5: /
0x6: /
0x7: /
0x8: SPI1 TX
0x9: /
0xA: Security System TX
26:25
24:23
22:21
20:16
R/W
R/W
R/W
R/W
A13 User Manual V1.3
Copyright © 2013 Allwinner Technology. All Rights Reserved.
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