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Memory controller RM0305 MEM38_CTL register MEM38_CTL is a read/write register used to configure the memory controller parameters. Table 204. MEM38_CTL register bit assignments MEM38_CTL register 0x098 Bit Name Reset value [31] rfu - [30:24] int_status 7h’0 [23] rfu - [22:16] int_mask 7h’0 [15:13] rfu - [12:08] trc 5h’0 [07:05] rfu - [04:00] tmrd 5h’0 270/712 Description Reserved for future use. Shows the status of all possible interrupts generated by the memory controller. The MSB is the result of a logical OR of all the lower bits. This parameter is read-only. The int_status bits correspond to these interrupts: – Bit 0: A single access outside the defined PHYSI-CAL memory space detected. – Bit 1: Multiple accesses outside the defined PHYSICAL memory space detected. – Bit 2: Port address range error detected. – Bit 3: DRAM initialization complete. – Bit 4: Address cross page boundary detected. – Bit 5: DLL unlock condition detected. – Bit 6: Logical OR of all lower bits. Reserved for future use. Active-high mask bits that control the value of the memory controller_int signal on the ASIC interface. This mask is inverted and then logically AND’ed with the outputs of the int_status parameter. Reserved for future use. Defines the DRAM period between active commands for the same bank, in cycles. Reserved for future use. Defines the DRAM mode register set command time, in cycles. Doc ID 022038 Rev 1
