Download XC161-32 - Infineon

XC161-32 Derivatives
System Units (Vol. 1 of 2)
Central Processing Unit (CPU)
SP
Stack Pointer Register
15
14
13
12
SFR (FE12H/09H)
11
10
9
8
7
6
Reset Value: FC00H
5
4
3
1
0
sp
0
rwh
r
Field
Bits
Type
Description
sp
[15:1]
rwh
Modifiable Portion of Register SP
Specifies the top of the system stack.
SPSEG
Stack Pointer Segment
2
SFR (FF0CH/86H)
7
6
Reset Value: 0000H
15
14
13
12
11
10
9
8
5
4
3
-
-
-
-
-
-
-
-
SPSEGNR
-
-
-
-
-
-
-
-
rw
2
1
Field
Bits
Type
Description
SPSEGNR
[7:0]
rw
Stack Pointer Segment Number
Specifies the segment where the stack is located.
0
Note: SPSEG and SP can be updated via any instruction capable of modifying a 16-bit
SFR. Due to the internal instruction pipeline, a write operation to SPSG or SP
stalls the instruction flow until the register is really updated. The instruction
immediately following the instruction updating SPSG or SP can use the new value.
Extreme care should be taken when changing the contents of the stack pointer
registers. Improper changes may result in erroneous system behavior.
User’s Manual
CPUSV2_X, V2.2
4-54
V1.0, 2004-02