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R8C/33C Group
7. I/O Ports
Table 7.18
Register
Bit
Port P1_5/RXD0/TRAIO/INT1
PD1
U0SR
TRASR
PD1_5 RXD0SEL0
Setting
Value
TRAIOC
TRAIOSEL
1
0
TOPCR
TRAMR
INTSR
TMOD
INT1SEL
2
1
0
2
1
0
INTEN
INTCMP
INT1EN INT1CP0
Function
0
X
Other than
10b
X
X
X
X
X
X
X
X
X
Input port (1)
1
X
Other than
10b
X
X
X
X
X
X
X
X
X
Output port (2)
0
1
Other than
10b
X
X
X
X
X
X
X
X
X
RXD0 input (1)
0
X
X
X
X
X
X
TRAIO input (1)
0
X
0
0
1
1
0
INT1 input (1)
0
X
1
0
0
0
0
1
1
0
TRAIO/INT1 input (1)
X
X
1
0
0
X
X
X
X
X
TRAIO pulse
output (2)
0
1
1
0
0
X
X
X
X
X
TRAIO/RXD0 input
(Hardware LIN)
0
0
1
1
0
TRAIO/RXD0/INT1
input
(Hardware LIN)
0
1
0
0
Other than
10b
1
1
Other than 000b,
001b
X
0
0
X
X
X
Other than 000b,
001b
0
0
1
Master mode: 000b
Slave mode: 011b
X: 0 or 1
Notes:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P1DRR5 bit in the P1DRR register to 1.
Table 7.19
Register
Bit
Setting
Value
Port P1_6/CLK0/IVREF1
PD1
PD1_6
U0SR
CLK0SEL0
U0MR
SMD
2
1
0
INTCMP
CKDIR
Function
INT1CP0
0
0
X
X
X
X
X
Input port (1)
1
0
X
X
X
X
X
Output port (2)
0
1
X
X
X
1
X
CLK0 (external clock) input (1)
X
1
0
0
1
0
X
CLK0 (internal clock) output (2)
0
0
X
X
X
X
1
Comparator B1 reference voltage input (IVREF1)
X: 0 or 1
Notes:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P1DRR6 bit in the P1DRR register to 1.
REJ09B0570-0100 Rev.1.00 Dec. 14, 2009
Page 88 of 589