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Freescale Semiconductor,EOnCE Inc.Module Internal Architecture Figure 4-6 shows a block diagram of the event counter. Count Value Internal Clock 31-bit Event Counter Inst Execution ECNT_VAL Count Event Event0-5 Count Selector EventD Trace Freescale Semiconductor, Inc... DEBUGEV EC0-1 31-bit Extension Counter Control Register ECNT_CTRL ECNT_EXT Figure 4-6. Event Counter Block Diagram 4.4.3 Event Detection Unit (EDU) The EOnCE EDU capabilities are: • Event detection on program and data memory address bus range or value • Event detection on data memory and data bus range or value • Detection of data written or read to/from a certain data memory address • Generating an EOnCE event upon event detection The EOnCE EDU includes six instances of an Address Event Detection Channel (EDCA), one Data Event Detection Channel (EDCD), and an event selector (ES). The possible events generated by the EDU are: • Entering the core into debug mode • Causing a debug exception • Enabling the trace buffer • Disabling the trace buffer SC110 DSP Core Reference Manual For More Information On This Product, Go to: www.freescale.com 4-13
