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Download SC110 DSP Core Reference Manual
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Freescale Semiconductor, Inc. Core Architecture Figure 2-11 illustrates the use of these instructions in the case of an unsigned integer double-precision multiplication of 32-bit by 32-bit unsigned operands. In this example, only a 32-bit result is generated. The most significant 32-bits are shifted out. All multiplications are of the “Unsigned x Unsigned” type using different combinations of high and low portions. D0.l D0.h × D1.h D1.l = Unsigned × Unsigned impyuu d0,d1,d2 D1.l × D0.l Freescale Semiconductor, Inc... Unsigned × Unsigned impyhluu d0,d1,d3 D0.h × D1.l imaclhuu d0,d1,d3 D1.h × D0.l + + aslw d3 0 D3.l add d2,d3 D3.h D3.l 32 bits Figure 2-11. Unsigned Integer Double-Precision Multiplication 2.2.2.9 Viterbi Decoding Support A set of DALU and AGU operations is provided for Viterbi decoding kernels. A special MAX2VIT operation is defined. This instruction functions as a regular MAX2 instruction and is used to transfer two 16-bit maximum signed values. In addition, the MAX2VIT instruction updates two Viterbi flags (VFs) which reside in the status register as described in Section 3.1.1, “Status Register (SR),” on page 3-1. Complementary AGU move operations are provided (VSL instructions). 2-30 SC110 DSP Core Reference Manual For More Information On This Product, Go to: www.freescale.com
