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Mihai V. MICEA Real-Time Data Acquisition and DSP Systems Figure 4-1. Block diagram of the SC140 core (source: [68]) XDBA XDBB 64 64 8 2 1 Shifter/Limiter 40 40 .. . . . 40 40 39 . 64 64 (8 buses) 32 31 16 15 0 L0 D0.e D0.h D0.l D0 L1 D1.e D1.h D1.l D1 L2 D2.e D2.h D2.l D2 L15 D15.e D15.h D15.l D15 DALU Register File 40 40 40 ALU 1 (4 x 3 buses) ... 2 3 4 Figure 4-2. DALU architecture High Performance Multiprocessor DSP Architectures 59