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MC2 Functions
LBTO
3
These bits define the local bus time-out value. The timer
begins timing when TS is asserted on the local bus. If TA
or TEA is not asserted before the timer times out, a TEA
signal is sent to the local bus. Note that Version register
bit V1 must be set to a 1 to enable the access timer in the
MC2 sector (i.e., it must be a "No VMEbus Interface"
option).
0
1
2
3
8 µs
64 µs
256 µs
The timer is disabled.
DRAM Control Register
This register enables access to the SDRAM array in the MC2 memory
model. Note that the SDRAM array is capable of single-bit error
correction and multi-bit error detection. The error correction mode is
enabled in the MC2 model by the added definitions of the RAMEN,
PAREN, and PARINT control bits.
ADR/SIZ
BIT
$FFF42048 (8 bits)
31
30
29
28
NAME
27
26
25
24
WWP
PARINT
PAREN
RAMEN
OPER
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
0
0
0
0
0 PL
0 PL
0 PL
0 PL
RAMEN
3-44
This bit enables the access of the DRAM. The DRAM
should be enabled after the DRAM Space Base Address
register is enabled and the ROM0 bit has been cleared.
The DRAM Space Base Address register is located at
$FFF42020 bits 31-16 and the ROM0 bit is located at
$FFF42040 bit 20.
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