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Programming Model
Error Logger Register
ADR/SIZ
BIT
1st $FFF4305C/2nd $FFF4315C (8-bits)
31
30
29
28
27
26
25
24
NAME
ERRLOG
ERD
ESCRB
ERA
EALT
0
MBE
SBE
OPER
R/C
R
R
R
R
R
R
R
RESET
0 PLS
0 PLS
0 PLS
0 PLS
0 PLS
X
0 PLS
0 PLS
SBE
SINGLE BIT ERROR is set when the last error logged
was due to a single-bit error. It is cleared when a 1 is
written to the ERRLOG bit. The syndrome code reflects
the bit in error. (Refer to the Syndrome Decoding section.)
MBE
MULTIPLE BIT ERROR is set when the last error logged
was due to a multiple bit error. It is cleared when a 1 is
written to the ERRLOG bit. The syndrome code is
meaningless if MBE is set.
ERA
This bit provides status for a function that is not currently
used in the MCECC sector.
EALT
EALT indicates that the last logging of an error occurred
on a DRAM access by an alternate (MI∗ not asserted)
local bus master.
ESCRB
ESCRB indicates the entity that was accessing DRAM at
the last logging of a single- or double-bit error. If ESCRB
is 1, it indicates that the scrubber was accessing DRAM.
If ESCRB is 0, it indicates that the local MC680x0 bus
master was accessing DRAM.
ERD
ERD reflects the state of the local bus READ signal pin at
the last logging of a single- or double-bit error. ERD = 1
corresponds to READ = high and ERD = 0 to READ =
low. ERD is meaningless if ESCRB is set.
ERRLOG When set, ERRLOG indicates that a single- or a doublebit error has been logged by this MCECC, and that no
more will be logged until it is cleared. The bit can only be
set by logging an error and cleared by writing a 1 to it.
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