Download Stellaris LM3S9B90 Evaluation Board User`s Manual (Rev. C)

Stellaris® LM3S9B90 Evaluation Kit User’s
Manual
User ’s Manual
EK-LM3S9B90 -0 5
Co pyrigh t © 2 009– 201 1 Te xas In strumen ts
Copyright
Copyright © 2009–2011 Texas Instruments, Inc. All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments.
ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property
of others.
Texas Instruments
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/stellaris
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July 5, 2011
Stellaris® LM3S9B90 Evaluation Kit User’s Manual
Table of Contents
Chapter 1: Stellaris® LM3S9B90 Evaluation Kit Overview ........................................................................... 7
Kit Contents ........................................................................................................................................................ 8
Using the EK-LM3S9B90.................................................................................................................................... 8
Features.............................................................................................................................................................. 8
Chapter 2: Hardware Description .................................................................................................................. 11
Evaluation Board .............................................................................................................................................. 11
Functional Description .................................................................................................................................. 11
In-Circuit Debug Interface Board ...................................................................................................................... 14
Functional Description .................................................................................................................................. 14
Chapter 3: Software Development ................................................................................................................ 17
Software Description......................................................................................................................................... 17
Source Code..................................................................................................................................................... 17
Tool Options ..................................................................................................................................................... 17
Programming the EK-LM3S9B90 Board........................................................................................................... 17
Appendix A: Schematics................................................................................................................................ 19
Appendix B: Connection Details ................................................................................................................... 25
Component Locations....................................................................................................................................... 25
Board Dimensions ............................................................................................................................................ 26
Board Connectivity............................................................................................................................................ 27
References ....................................................................................................................................................... 27
Appendix C: Microcontroller GPIO Assignments ........................................................................................ 29
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List of Figures
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure B-1.
Figure B-2.
Figure B-3.
Figure B-4.
Figure B-5.
4
LM3S9B90 Evaluation Board .......................................................................................................... 7
In-Circuit Debug Interface Board..................................................................................................... 7
EK-LM3S9B90 Evaluation Board Block Diagram.......................................................................... 11
GPIO Pads .................................................................................................................................... 12
JTAG/SWD Connector .................................................................................................................. 12
PWR/UART Connector.................................................................................................................. 13
In Circuit Debug (ICDI) Board Block Diagram ............................................................................... 14
JTAG/SWD Connector J1 ............................................................................................................. 15
JTAG/SWD Connector J3 ............................................................................................................. 15
PWR/UART Connector.................................................................................................................. 15
EK-LM3S9B90 Evaluation Board Component Locations .............................................................. 25
BD-ICDI Board Component Locations .......................................................................................... 25
EK-LM3S9B90 Evaluation Board Dimensions .............................................................................. 26
In-Circuit Debug Interface Board Dimensions ............................................................................... 26
ICDI – EK-LM3S9B90 Board Connectivity .................................................................................... 27
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List of Tables
Table C-1. EK-LM3S9B90 Evaluation Board GPIO Usage............................................................................. 29
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C H A P T E R 1
Stellaris® LM3S9B90 Evaluation Kit Overview
Texas Instruments' Stellaris® LM3S9B90 Evaluation Board Kit (EK-LM3S9B90) is a low-cost
platform for evaluation of the LM3S9B90 microcontroller. The kit includes two boards, the
EK-LM3S9B90 evaluation board, and the In-Circuit Debug Interface (BD-ICDI) board.
The EK-LM3S9B90 board includes the LM3S9B90 ARM® Cortex™-M3 Microcontroller, a 10/100
Mbit Ethernet port, a full-speed USB-OTG port, connectors for inteface to the BD-ICDI board, and
oversized pads for easy connection to the microcontroller GPIO ports.
The BD-ICDI board is a USB full-speed JTAG/SWD debugger board. It includes a USB miniB
connector for connection to a USB PC port, and two shrouded header connectors for connection to
the EK-LM3S9B90 board.
Development of software for the EK-LM3S9B90 is simplified by using Texas Instruments’
comprehensive StellarisWare® peripheral driver library and ARM development tools from our tools
partners. The Stellaris® LM3S9B90 Evaluation Board Kit includes the two boards described, a
documentation CD, and cables. All design files are provided on the EK-LM3S9B90 CD.
Figure 1-1.
LM3S9B90 Evaluation Board
Figure 1-2.
In-Circuit Debug Interface Board
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Stellaris® LM3S9B90 Evaluation Kit Overview
Kit Contents
The EK-LM3S9B90 evaluation kit comes with the following:
„
EK-LM3S9B90 evaluation board
„
In-Circuit Debug Interface (BD-ICDI) board
– Connects to USB port on PC and to 10-pin, fine-pitch ARM JTAG connector on the
EK-LM3S9B90 evaluation board
– Secondary 8-pin Power/UART connector provides power and virtual comm-port capability
to the EK-LM3S9B90 evaluation board.
„
Cables
– USB miniB to USB-A cable
– USB-OTG to USB-A cable
– 10-pin ribbon cable for JTAG/SWD connection
– 8-pin ribbon cable for Power/UART connection
„
CD containing:
– A supported version of one of the following (including a toolchain-specific Quickstart
guide):
•
Keil™ RealView® Microcontroller Development Kit (MDK-ARM)
•
IAR Embedded Workbench
•
Sourcery CodeBench development tools
•
Code Red Technologies development tools
•
Texas Instruments’ Code Composer Studio™ IDE
– Complete documentation
– Quickstart application source code
– Stellaris® Firmware Development Package with example source code
Using the EK-LM3S9B90
The recommended steps for using the EK-LM3S9B90 evaluation kit are:
1. Follow the Quickstart guide included in the kit. The Quickstart guide will help get the
EK-LM3S9B90 Evaluation Board up and running in minutes.
2. Use your preferred ARM tool-chain and the Stellaris Peripheral Driver Library to
develop an application. Software applications are loaded using the BD-ICDI board. See
Chapter 3, “Software Development,” for the programming procedure. The StellarisWare
Peripheral Driver Library Software Reference Manual contains specific information on
software structure and function.
3. Customize and integrate the hardware to suit an end application. This user's manual is an
important reference for understanding circuit operation and completing hardware modification.
Features
The EK-LM3S9B90 evaluation kit provides the following features:
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Stellaris® LM3S9B90 Evaluation Kit User’s Manual
„
LM3S9B90 high-performance Stellaris microcontroller and large memory
– 32-bit ARM® Cortex™-M3 core
– 256 KB single-cycle Flash memory, 96 KB single-cycle SRAM
„
Ethernet 10/100 port with two LED indicators
„
USB 2.0 Full-Speed OTG port
„
Virtual serial communications port capability
„
Oversized board pads for GPIO access
„
User pushbutton and LED
„
Detachable ICDI board can be used for debugging other Stellaris boards
„
Easy to customize
– Includes full source code, example applications, and design files
– Develop using tools supporting FastMATH from Keil, IAR, Code Sourcery, and Code Red
(using a Stellaris evaluation kit or preferred ARM Cortex-M3 debugger)
– Supported by Texas Instruments’ StellarisWare peripheral driver library
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Stellaris® LM3S9B90 Evaluation Kit Overview
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C H A P T E R 2
Hardware Description
The EK-LM3S9B90 evaluation kit contains two boards: the EK-LM3S9B90 evaluation board and
the BD-ICDI JTAG debug board as described in more detail in this chapter.
Evaluation Board
The EK-LM3S9B90 evaluation board uses the Stellaris® LM3S9B90 microcontroller and includes
a 10/100 Ethernet port and a USB 2.0 full-speed OTG port. The board is intended for use with the
ICDI board, but can be used as a standalone board as well. Figure 2-1 shows the block diagram.
Figure 2-1.
EK-LM3S9B90 Evaluation Board Block Diagram
Ethernet 10/100
BOARD PADs
GPIOs
Ethernet
25MHz
RESET
USER LED
Stellaris
LM3S9B90
JTAG/SWD
USER PUSHBUTTON
JTAG
USB – OTG
USB
USB Power
Switch
PWR/UART
UART0
MOSC
16MHz
RTC
4.19MHz
5V
VBUS
DPDT
3.3V
Regulator
Functional Description
Microcontroller, Reset, GPIO Pads, and JTAG (Schematic page 20)
Microcontroller
The evaluation board uses the Stellaris LM3S9B90 microcontroller. A 16 MHz crystal provides the
main oscillator clock which can directly drive the ARM core clock or can drive an internal PLL to
increase the core clock up to 80 MHz. A 25 MHz crystal is used for the Ethernet clock and a
4.194304 MHz crystal is used for the real-time clock.
The LM3S9B90 microcontroller has an internal LDO voltage regulator that supplies power for
internal use. This rail requires only three capacitors for decoupling and is not connected to any
other circuits.
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Hardware Description
Reset
A reset switch and R-C network connects to the microcontroller’s RSTn input. The reset signal is
also connected to the JTAG/SWD connector J1 to allow reset control from the debugger.
GPIO Pads
Four groups of oversized board pads with a 0.1” spacing provide access to GPIO signals and
standard 0.1” pitch headers can be soldered to these pads. Pads are labeled with the
corresponding GPIO signal, and pads with no labels are unconnected. Note that GPIO signals
required for operation of the Ethernet port, USB port, and JTAG port are reserved for board use
and are not available on these pads. Figure 2-2 shows the pad groups.
GPIO Pads
PG
0
2
PJ
0
PJ
PJ
GN
D
PA
7
PA
6
PA
5
PA
4
PA
3
PA
2
V
GN
D
3.3
PF
5
PF
4
PF
3
PF
2
PF
0
PE
0
PE
1
PE
2
PE
3
PE
4
PE
5
PE
6
PE
7
R
PB
2
PB
3
PB
4
PB
5
PB
6
PB
7
GN
D
GPIO Pads – Bottom right
5V
PA
1
PA
0
5V
GPIO Pads – Bottom left
1
PG
7
VB
US
PH
0
PH
1
PH
2
PH
5
PH
6
PH
7
PG
1
7
6
PD
5
PD
4
PD
GPIO Pads – Top right
HI
B
W
AK
E
VB
AT
3
PD
2
PC
7
SH
DN
PD
1
PD
PC
6
PD
PC
5
PC
4
PD
0
GPIO Pads – Top left
PF
1
Figure 2-2.
GPIO Jumpers
Some of the GPIO signals used by the board are connected to board jumpers and can be
disconnected to provide additional user GPIOs. GPIOs PA0/PA1/PB4/PD0/PF2/PF3 are
connected to jumpers JR1-JR6 respectively. Each signal can be freed by cutting the trace of the
corresponding jumper (cut at white line on silkscreen). The jumper pads have the same footprint
as an 0603 SMT resistor. To reconnect a previously cut jumper, solder a 0 ohm resistor to the
corresponding jumper footprint.
JTAG/SWD
The JTAG/SWD connector J1 is used for program download and debug. This is a 2x5 fine pitch
(0.050”) ARM JTAG connector, see (Figure 2-3) for signal definition. The LM3S9B90
microcontroller supports JTAG debug, Serial Wire Debug (SWD), and Serial Wire Out (SWO) trace
with this connector. The ICDI board connects via a 10-wire ribbon cable to this connector.
Figure 2-3.
JTAG/SWD Connector
10 9
In
RSTn
In
TDI
Out
TDO/SWO
In
TCK/SWCLK
I/O TMS/SWDIO
GND
N/C
GND
GND
3.3V Out
2 1
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Stellaris® LM3S9B90 Evaluation Kit User’s Manual
PWR/UART
The PWR/UART connector J2 is used to provide 5 V power from the ICDI board and also to
connect the LM3S9B90 UART0 signals. This is a 2x4 fine pitch (0.050") connector, see
(Figure 2-4) for signal definition. The UART0 signals are connected to GPIO jumpers JR1 and JR2
and can be disconnected from connector J2 if required, see “GPIO Jumpers” on page 12. The
ICDI board connects via an 8-wire ribbon cable to this connector.
Figure 2-4.
PWR/UART Connector
8 7
Out
Out
In
5V
DBG2
VCP_RX
VCP_TX
5V
DBG1
GND
GND
Out
2 1
Ethernet, USB, Power and Miscellaneous (Schematic page 21)
Page 2 of the schematics contains the Ethernet RJ45 connector, USB power switch and USB OTG
connector, 3.3 V regulator, and power switch selector.
Ethernet Port
The on-board RJ45 connector provides a 10/100 base T Ethernet port. The RJ45 connector
includes integrated LEDs and magnetics. The LEDs are connected to GPIO jumpers JR4 and JR5
and can be disconnected from the RJ45 connector if required, see GPIO Jumpers section.
USB Port
The on-board USB microAB connector provides a USB 2.0 full-speed port. To use as an On-TheGo (OTG) port, the power selector switch SW3 lever must be set to EXT. This selects an external
5 V power source to provide power to the board and the USB power switch. If the SW3 lever is set
to USB, power to the board is received from USB, the on-board USB power switch output is
disconnected from USB, and the board can only be used as a USB device. When using the
USB-OTG port in Host mode, the current provided to a USB device should be limited to 100 mA or
less when powered from the ICDI board. If powered from the 5 V test pad, then this can be
increased to 500 mA.
Board Power
The board requires 5 V for operation, and switch SW3 is used to select the power source. If the
switch lever is moved towards the USB label on the board, power is received from the USB
connector. If the switch lever is moved towards the EXTernal board label, the board is powered
from the PWR/UART connector and the ICDI board provides power to this connector. DC regulator
U2 generates 3.3 V for powering the board circuits and includes power indicator LED D1.
User Devices
Pushbutton switch SW2 and LED D2 are available for the user and connected to PB4 and PD0
respectively. These GPIOs are connected to GPIO jumpers JR3 and JR4 and can be
disconnected from SW2 and D2 if required, see GPIO Jumpers section.
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Hardware Description
In-Circuit Debug Interface Board
The ICDI board is used to download and debug programs on the EK-LM3S9B90 evaluation board,
but can also be used for debug of other Stellaris boards. A block diagram is shown in Figure 2-5.
Figure 2-5.
In Circuit Debug (ICDI) Board Block Diagram
JTAG/SWD
USB
2x10
USB
JTAG/SWD
2x5
PortA
PortB
JTAG/SWD
MUX
FTDI
EEPROM
PWR /UART
2x4
DEBUG
ACTIVE
OSC
6MHz
VBUS
RESET
POWER
3.3V
Regulator
Functional Description
USB to JTAG/SWD, Power (Schematic page 22)
USB
An FTDI USB to serial protocol chip is used for the USB 2.0 full-speed device controller. This is
connected to a USB miniB connector and to a set of buffers/multiplexers. A 1-kbit serial EEPROM
contains USB configuration data which is read at power up.
Power
The board receives 5 V power from the USB bus. A DC regulator generates 3.3 V for on-board
circuits, when on LED D1 (POWER) is lit on.
Headers
Three headers are on-board, a 10-pin JTAG/SWD header J1, an 8-pin PWR/UART header J2, and
an optional 20-pin JTAG/SWD header J3. The 10-pin and 8-pin headers are used to connect to the
EK-LM3S9B90 evaluation board.
JTAG/SWD
JTAG/SWD connector J1 connects to the EK-LM3S9B90 evaluation board with a ribbon cable for
program download and debug. This is a 2x5 fine pitch (0.050”) ARM JTAG connector, see
(Figure 2-6) for signal definition.The ICDI supports JTAG debug, SWD (Serial Wire Debug), and
SWO (Serial Wire Out) trace with this connector.
Optional JTAG/SWD connector J3 is a 2x10 standard pitch (0.1”) ARM JTAG connector directly
connected to J1, see (Figure 2-7) for signal definition. This allows the ICDI to connect to targets
that use a 2x10 connector. It also allows the use of an external 2x10 debugger on targets with the
fine pitch connector, including the EK-LM3S9B90. The signal direction shown for J1 and J3 applies
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Stellaris® LM3S9B90 Evaluation Kit User’s Manual
when the ICDI is used as the JTAG/SWD debugger and LED D2 (DEBUG ACTIVE) is lit on. In this
case only one of the two connectors J1/J3 should be used.
The ICDI can also be used as a 20-pin to 10-pin adapter for external JTAG debuggers. Note that
the DEBUG ACTIVE LED must be off before connecting any external JTAG debuggers.
Figure 2-6.
JTAG/SWD Connector J1
10 9
Out
SRSTn
Out
TDI
In
TDO/SWO
Out TCK/SWCLK
I/O TMS/SWDIO
GND
N/C
GND
GND
VSENSE In
2 1
Figure 2-7.
JTAG/SWD Connector J3
20
19
GND
GND
GND
GND
GND
GND
GND
GND
GND
N/C
N/C
N/C
SRSTn
TDO/SWO
N/C
TCK/SWCLK
TMS/SWDIO
TDI
N/C
VSENSE
2
Out
In
Out
I/O
Out
In
1
Pushbutton
Pushbutton SW1 (RESET) is provided to manually generate the SRSTn signal to the target
device. The SRSTn signal can also be generated under program control.
PWR/UART
The PWR/UART connector J2 connects to the EK-LM3S9B90 evaluation board with a ribbon cable
and provides 5 V power and a virtual communications port connection. This is a 2 x 4 fine pitch
(0.050”) connector, see (Figure 2-8) for signal definition. Signals DBG1/DBG2 are reserved.
Figure 2-8.
PWR/UART Connector
8 7
Out
Out
In
5V
DBG2
VCP_RX
VCP_TX
5V
DBG1
GND
GND
Out
2 1
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Hardware Description
JTAG / SWD Multiplexer (Schematic page 23)
Buffers
A set of tri-state buffers is used to multiplex JTAG and SWD signals, and also multiplex the UART
VCP_TX signal with the SWO signal. LED D2 (DEBUG ACTIVE) is lit on when these buffers are
enabled. To avoid signal contention, external JTAG debuggers should not be connected when
DEBUG ACTIVE is on.
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C H A P T E R 3
Software Development
This chapter provides general information on software development as well as instructions for
Flash memory programming.
Software Description
The software provided with the EK-LM3S9B90 provides access to all of the peripheral devices
supplied in the design. The StellarisWare® Peripheral Driver Library is used to operate the on-chip
peripherals.
The software includes a set of example applications that utilize the StellarisWare Peripheral Driver
Library. These applications demonstrate the capabilities of the LM3S9B90 microcontroller, as well
as providing a starting point for the development of the final application for use on the
EK-LM3S9B90.
Source Code
The complete source code is included on the EK-LM3S9B90 CD. Refer to the Quickstart Guide for
a detailed description of hardware setup and how to install the source code. The source code and
binary files are installed in the DriverLib tree.
Tool Options
The source code installation includes directories containing projects and/or makefiles for the
following tool-chains:
„
Keil ARM RealView® Microcontroller Development System
„
IAR Embedded Workbench for ARM
„
CodeSourcery G++
„
Code Red Technology Red Suite
„
Generic Gnu C compiler
Evaluation versions of these tools may be downloaded from www.ti.com/stellaris. Due to code size
restrictions, the evaluation tools may not build all example programs. A full license is necessary to
re-build or debug all examples.
Instructions on installing and using each of the evaluation tools can be found in the Quickstart
guides (for example, Quickstart-Keil, Quickstart-IAR) which are available for download from the
evaluation kit section of our web site at www.ti.com/stellaris.
For detailed information on using the tools refer to the documentation included in the tool chain
installation or visit the website of the tools supplier.
Programming the EK-LM3S9B90 Board
The EK-LM3S9B90 software package includes pre-built binaries for each of the example
applications. If you installed DriverLib to the default installation path of C:/DriverLib, you can find
the example applications in “C:/DriverLib/boards/ek-tempest”. The ICDI board is used along with
Stellaris LM Flash Programmer tool to program applications on the EK-LM3S9B90 board.
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17
Software Development
To program example applications into the EK-LM3S9B90 evaluation board using the ICDI
board:
1. Install LM Flash Programmer on a Windows PC.
2. Connect the 10-wire ribbon cable to the 10-pin header on the ICDI board and to the 10-pin
header on the EK-LM3S9B90 board. The red stripe on the ribbon cable should be facing the
bottom of the connectors (see Figure B-5 on page 27).
3. Connect the 8-wire ribbon cable to the 8-pin header on the ICDI board and to the 8-pin header
on the EK-LM3S9B90 board. The red stripe on the ribbon cable should be facing the bottom of
the connectors (see Figure B-5 on page 27).
4. Verify that slide switch SW3 on the EK-LM3S9B90 board is set to EXTernal.
5. Connect the USB cable A-plug to an available port on the PC and the miniB-plug to the ICDI
board.
6. Verify that POWER LED D1 on the ICDI board is lit and POWER LED D1 on the
EK-LM3S9B90 board is also lit.
7. Run LM Flash Programmer.
8. In the Configuration tab, use the Quick Set control to select LM3S9B90 Evaluation Board.
9. Move to the Program tab and click the Browse button. Navigate to the example applications
directory (the default location is “C:/DriverLib/boards/ek-tempest/).
10. Each example application has its own directory. Navigate into the example directory that you
want to load and then into the directory which contains the binary (*.bin) files. Select the binary
file and click Open.
11. Set the “Erase Method” to “Erase Necessary Pages” and check the “Verify After Program” box.
12. Next, click the Program button to start the Erase, Download and Verify process. The DEBUG
ACTIVE LED (D2) on the ICDI will turn on at this time.
13. Program execution will start once Verify is complete.
The EK-LM3S9B90 design uses a Stellaris® LM3S9B90 microcontroller to handle networking,
USB-OTG, and peripheral functions. The entire circuit is built on a compact four-layer printed
circuit board. All design files are provided on the EK-LM3S9B90 CD.
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A P P E N D I X A
Schematics
This section contains the schematics for the EK-LM3S9B90 evaluation board and also the
BD-ICDI debug board.
EK-LM3S9B90 Evaluation Board
„
Microcontroller, Reset, and Headers on page 20
„
Ethernet, USB, and Power on page 21
BD-ICDI Board
July 5, 2011
„
USB to JTAG, SWD, Headers, and Power on page 22
„
JTAG/SWD Multiplexer on page 23
19
Microcontroller, Reset, and Headers
1
2
3
4
5
6
Revision History
VBUS
Revision
Date
A
2/24/2009
First release for prototypes.
B
4/15/2009
Released to production.
U1
10K
10K
10K
10K
3.3V
J1
1
3
5
7
9
C1
0.1uF
2
4
6
8
10
TMS
TCK
TDO
TDI
RSTn
HDR 2X5-MH-SHRD
5V JTAG/SWD
J2
8
6
4
2
DBG2
VCP_RX
VCP_TX
7
5
3
1
DBG1
HDR 2X4-MH-SHRD
PWR/UART
26
27
28
29
30
31
34
35
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
80
79
78
77
25
24
23
22
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
74
75
95
96
6
5
2
1
PG0
PG1
XTALN
XTALP
PF5
PG7
19
18
17
16
41
40
37
36
OSCin
OSCout
48
49
B
ETH_RXIP
ETH_RXIN
3.3V
HIBn
R24
10K
3.3V
PA0/U0RX
PA1/U0TX
PA2/SSI0CLK
PA3/SSI0FSS
PA4/SSI0RX
PA5/SSI0TX
PA6
PA7
PC0/TCK/SWCLK
PC1/TMS/SWDIO
PC2/TDI
PC3/TDO/SWO
PC4
PC5
PC6
PC7
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PG0
PG1
XTALNPHY
XTALPPHY
PF5
RXIP
RXIN
PG7
OSC0
OSC1
4
3
1
2
RESET
R23
51
10
RSTn
33
C2
C
64
0.1uF
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PF0
PF1
PF2/LED1
PF3/LED0
MDIO
TXON
TXOP
PF4
PH0
PH1
PH2
PH3/USB0EPEN
PH4/USB0PFLT
PH5
PH6
PH7
HIB
PJ0
PJ1
PJ2
WAKEn
XOSC0
XOSC1
GND
VBAT
RST
USB0DP
USB0DM
SW1
R6
10K
PB0/USB0ID
PB1/USB0VBUS
PB2/I2C0SCL
PB3/I2C0SDA
PB4
PB5
PB6
PB7
ERBIAS
USB0RBIAS
Y2
GND
GND
GND
GND
GND
GND
GND
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
CVDD
CVDD
Y1
1
2
4
25.000 MHz
C15
18pF
16.000 MHz
C16
18pF
10
11
12
13
97
98
99
100
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
47
61
60
59
58
46
43
42
PF0
PF1
PF2
PF3
86
85
84
83
76
63
62
15
PH0
PH1
PH2
14
87
39
50
52
53
54
55
PJ0
PJ1
PJ2
C
1/21/2010
DC regulators U2 and U4 replaced for TI parts.
6/17/2011
Add option to install either LM3S9B90 or LM3S9D90
C17
18pF
C18
18pF
AGND
AVDD
LM3S9B90/LM3S9D90
D
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC4
PC5
PC6
PC7
HIBn
WAKEn
VBAT
PF4
USBPWR
USBFLT
PH5
PH6
PH7
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PG0
PJ0
PJ1
PJ2
3.3V
R5
10K
WAKEn
R7
C3
0.1uF
8
20
32
44
56
68
81
93
PF0
PF1
PF2
PF3
PF4
PF5
B
3.3V
VBUS
PG1
PG7
PH0
PH1
PH2
PH5
PH6
PH7
C4 4.194304 MHz
18pF
3.3V
7
38
88
FB1
JR1
VCP_RX
PA1
JR2
VCP_TX
PB4
JR3
PD0
JR4
PF2
JR5
PF3
JR6
Y3
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
C11
0.1uF
C12
0.1uF
C13
0.1uF
C14
0.1uF
C5
18pF
USR_PBn
C
USR_LED
ETH_LED1
ETH_LED0
C6
1uF
TI AEC - Austin
CVDD
C19
0.1uF
C20
0.1uF
108 Wild Basin Rd.
Suite 350
Austin, TX 78746
C22
Designer:
Drawing Title:
Page Title:
Tempest, Reset, Test Pads
Size
Document Number:
B
*
Date:
4
D
EK-LM3S9B90 and EK-LM3S9D90 Evaluation Board
Arnaldo Cruz
1uF
Approved:
July 5, 2011
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PA0
1M
Arnaldo Cruz
3
TP52
TP53
TP54
TP55
TP56
TP57
TP58
TP59
TP60
TP61
TP62
TP63
TP64
TP65
TP66
TP67
TP68
A
PB2
PB3
PB4
PB5
PB6
PB7
XOSC1
Drawn by:
2
TP35
TP36
TP37
TP38
TP39
TP40
TP41
TP42
TP43
TP44
TP45
TP46
TP47
TP48
TP49
TP50
TP51
5VR
9.1k
C23
0.1uF
1
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
XOSC0
USBDP
USBDM
VBAT
3
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
SHDNn
ETH_MDIO
ETH_TXON
ETH_TXOP
71
70
73
5V
R9
LDO
2
PB2
PB3
PB4
PB5
PB6
PB7
USBID
R8
12.4K
9
21
45
57
69
82
94
1
66
67
72
65
92
91
90
89
120ohm @ 100 MHz
R1
R2
R3
R4
A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Description
5
Rev
0001
6/17/2011
C
Sheet
1
of
2
6
20
Ethernet, USB, and Power
11
22
3
4
55
66
Revision History
3.3V
USB Micro AB
VBUS
Revision
Date
A
2/24/2009
First release for prototypes.
B
4/15/2009
C
1/21/2010
Released
production.
R10
R11 to
R12
R13
R14
10K 330
330
DC regulators U2 49.9
and U4
replaced
49.9
6/17/2011
Add option to install either LM3S9B90 or LM3S9D90
U1
FB2
120ohm @ 100 MHz
J1
C1
0.1uF
1
USBDM
3
USBDP5
USBID7
9
2
4
6
8
10
TMS
TCK
TDO
TDI
RSTn
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
HDR 2X5-MH-SHRD
5V JTAG/SWD
3.3V
J2
1
8
6
4
2
DBG1
3
2
R15
10K
7
5
3
1
4
SW2
DBG2
USR PB
VCP_RX
VCP_TX
USR_PBn
HDR 2X4-MH-SHRD
PWR/UART
BB
ETH_RXIP
ETH_RXIN
VBUS
3.3V
5V
1 SW3
HIBn
2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
74
75
95
96
6
5
2
1
PG0
PG1
XTALN
XTALP
PF5
PG7
19
18
17
16
41
40
37
36
OSCin
OSCout
48
49
6 R6
10K
Switch DPDT
4
3
1
5
PB0/USB0ID
PB1/USB0VBUS
PB2/I2C0SCL
PB3/I2C0SDA
PB4
PB5
PB6
PB7
ETH_MDIO
PD0
ETH_TXOP PD1
ETH_TXON PD2
PD3
PD4
PD5
PD6
PD7
ETH_RXIP
ETH_RXIN PF0
PF1
PF2/LED1
PF3/LED0
ETH_LED1MDIO
ETH_LED0TXON
TXOP
PF4
R18
330
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
D2
GREEN_LED
USR
PG0
PG1
XTALNPHY
XTALPPHY
PF5
RXIP
RXIN
PG7
PH0
PH1
PH2
PH3/USB0EPEN
PH4/USB0PFLT
PH5
PH6
PH7
OSC0
OSC1
PJ0
PJ1
PJ2
WAKEn
XOSC0
XOSC1
GND
VBAT
5
SW1
2
G2
G
PA0/U0RX
PA1/U0TX
PA2/SSI0CLK
PA3/SSI0FSS
PA4/SSI0RX
FB3
PA5/SSI0TX
120ohm @ 100 MHz
PA6
PA7
ID
80
PC0/TCK/SWCLK
79
PC1/TMS/SWDIO
78
PC2/TDI
77
PC3/TDO/SWO
25
PC4
24
PC5
USR_LED
23
PC6
22
PC7
R24
10K
3
3.3V
4
RESET
27
28
29
30
31
34
35
R23
51
10
RSTn
5V
C2
CC
64
33
0.1uF
HIB
3.3V
R19
10K
RST
ERBIAS
USB0RBIAS
USBPWR
R22
10K
C36
C37
4.7uF
0.1uF
9
21
45
57
69
82
94
GND
GND
GND
GND
GND
GND
GND
VDD33
VDD33
VOUT
VDD33
VDD33
VDD33
VDD33
VDD33
C38
VDD33
U3
5
4
2
VIN
VOUT
EN
OC
1
3
10
11
12
13
97
98
99
100
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
47
61
60
59
58
46
43
42
PF0
PF1
PF2
PF3
86
85
84
83
76
63
62
15
PH0
PH1
PH2
14
87
39
50
52
53
54
55
PJ0
PJ1
PJ2
LDO
Y2
CVDD
CVDD
Y1
2
1
2
4
25.000 MHz
16.000 MHz
C16
18pF
C17
18pF
C18
18pF
AGND
CVDD
U4
1
VIN
VOUT
C27
10pF
GND
FB
4
5
4
C28
10pF
7
R26
10
6
2
1
ETH_MDIO
ETH_TXON
ETH_TXOP
R16
49.9
USBPWR
USBFLT
R17
49.9
C29
10pF
Y-
PE0
Y+
PE1
PE2
9
NC
PE3
10
GND
PE4
PE5
PE6
PulseJack_RJ45_SMT
PE7
PG0
PJ0
C32
PJ1
0.01uF
PJ2
C30
10pF
3.3V
C31
0.1uF
R5
10K
5VR
SHDNn
3.3V
9.1k
R21
8
20
32
44
56
68
81
93
10K
C3
0.1uF
C33
4.7uF
U2
XOSC1
8
VIN
VOUT
2
NC
NC
5 VBAT
EN
NC
TPAD
TPAD
4
GND
NR
7
FB1
R9
Y3
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
C11
0.1uF
C12
0.1uF
C13
0.1uF
C14
0.1uF
C19
0.1uF
C20
0.1uF
FID2
40 Mil Pad
100 Mil Mask
VCP_RX
JR2
VCP_TX
PB4
JR3
PD0
JR4
PF2
JR5
C5 GREEN_LEDPF3
18pFPWR
JR6
R20
330
D1
FID3
40 Mil Pad
100 Mil Mask
USR_PBn
CC
USR_LED
ETH_LED1
ETH_LED0
C22
108 Wild Basin Rd.
Suite 350
Austin, TX 78746
Designer:
Drawing
Drawing Title:
Title:
Drawn by:
Page
Page Title:
Title:
Tempest,
Test Pads
Ethernet,Reset,
USB, Power
Size
Size
Document
Document Number:
Number:
B
Date:
Date:
4
D
D
EK-LM3S9B90
EK-LM3S9B90and
andEK-LM3S9D90
EK-LM3S9D90Evaluation
EvaluationBoard
Board
Arnaldo Cruz
1uF
*
July 5, 2011
PH0
PH1
PH2
PH5
PH6
PH7
TI AEC - Austin
CVDD FID1
Approved:
3
VBUS
PG1
PG7
C6
1uF
Arnaldo Cruz
22
BB
3.3V
ETHERNET 10/100
JR1
C35
4.194304 MHz
C4
0.1uF
18pF
Fiducials
11
PF0
PF1
PF2
PF3
PF4
PF5
PA1
1M
C34
4.7uF
3
TPS73633DRB
40 Mil Pad
100 Mil Mask
C23
0.1uF
TP52
TP53
TP54
TP55
TP56
TP57
TP58
TP59
TP60
TP61
TP62
TP63
TP64
TP65
TP66
TP67
TP68
PA0
1
7
6
3.3V
3
TP35
TP36
TP37
TP38
TP39
TP40
TP41
TP42
TP43
TP44
TP45
TP46
TP47
TP48
TP49
TP50
TP51
XOSC0
USBDP
USBDM
38
88
A
A
8
WAKEn
R7
5VR
8
SHDNn
PH5
PH6
PH7
Note:
U4 required only for LM3S9B90-B1.
See errata. Do not install for all
other devices/revisions.
TPS73101
D
D
10
5V
PA0
TP1 TP18
PA1Note:
TP2 TP19
PA2R25-R26 = 10 ohms for LM3S9B90-B1, see errata.PB2
TP3
TP20
R25-R26
=
0
ohms
for LM3S9B90-C.
PA3
PB3
TP4 TP21
J6 PA4
PB4
TP5 TP22
PA5
PB5
TP6 TP23
G+
PA6
PB6
TP7 TP24
GPA7
PB7
TP8 TP25
TP9 TP26
1CT:1
PC4
PD0
TP10 TP27
PC5
PD1
TP11 TP28 TX+ 1
PC6
PD2
TXTP12 TP29
2
PC7
PD3
TP13 TP30 RX+ 3
PD4
TP14 TP31
4
PD5
HIBn
TP15
TP32
5
1CT:1
PD6
WAKEn
TP16 TP33 RX- 6
PD7
VBAT
TP17 TP34
7
3
PF4
5
LM3S9B90/LM3S9D90
3
EN
2
AVDD
C26
0.01uF
for TI parts.
R25
71
70
73
C25
0.1uF
12
11
4.7uF
GND
TPS2051B
C15
18pF
PB2
PB3
PB4
PB5
PB6
PB7
USBID
R8
12.4K
USBFLT
1
USB0DP
USB0DM
66
67
72
65
92
91
90
89
120ohm @ 100 MHz
3.3V
D+
26
4
10K
10K
10K
10K
D-
3
R1
R2
R3
R4
A
A
VBUS
2
PA0
PA1
PA2
PA3
PA4
VUSBPA5
PA6
PA7
1
G1
VBUS
Description
GL
GR
J5
55
Rev
Rev
CC
0001
0001
6/17/2011
6/17/2011
Sheet
Sheet 12
of
of
22
66
21
USB to JTAG, SWD, Headers, and Power
11
22
3
4
55
Revision History
Revision History
D-
D+
TMS
TCK
TDO
TDI
RSTn
HDR 2X5-MH-SHRD
5V JTAG/SWD
J2
8
6
4
2
7
5
3
1
DBG1
R8
10K
HDR 2X4-MH-SHRD
U2 PWR/UART
8
1
VCC
CS
7
2
NC
SK
6
3
ORG
DI
5
4
GND
DO
BB
C2
0.1uF
R9
CAT93C46
ETH_RXIP
ETH_RXIN
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
74
75
95
96
6
5
2
1
PG0
PG1
XTALN2.21k
XTALP
PF5
PG7
19
18
17
16
41
40
37
36
OSCin
OSCout
48
49
1K 64X16
3.3V
HIBn
R24
10K
3.3V
4
3
1
2
C1
0.1uF
6
PC0/TCK/SWCLK
R5
27
PC1/TMS/SWDIO
PC2/TDI
R6
27
PC3/TDO/SWO
PC4
PC5
PC6
PC7
5V
PE0
PE1R10
PE210K
PE3
PE4
PE5
PE6
PE7
UDM
8
UDP
7
R7
1.50k
EECS
EESK
PG0
EEDATA
PG1
XTALNPHY
XTALPPHY
XTI
PF5
XTO
RXIP
RXIN
PG7
1
R6
10K
R23
2
OSC0
OSC1
C7
RSTn
18pF
0.1uF
3
Y2
10K
2
2
C11
25.000 MHz
4.7uF
First release for prototypes.
66
PB0/USB0ID
67
PB1/USB0VBUS
72
PB2/I2C0SCL
65
PB3/I2C0SDA
U1
92
PB4
91
PB5
90
PB6ADBUS0
89
3V3OUT
PB7ADBUS1
ADBUS2
10
PD0ADBUS3
11
USBDM
PD1ADBUS4
12
PD2ADBUS5
13
USBDP
ADBUS6
PD3
97
PD4ADBUS7
98
PD5
99
PD6ACBUS0
100
PD7ACBUS1
ACBUS2
47
PF0ACBUS3
61
PF1SI/WUA
60
PF2/LED1
59
PF3/LED0BDBUS0
58
MDIOBDBUS1
46
TXONBDBUS2
43
TXOPBDBUS3
42
PF4BDBUS4
EECS
BDBUS5
86
EESK
PH0BDBUS6
85
EEDATA
PH1BDBUS7
84
TEST
PH2
83
PH3/USB0EPENBCBUS0
76
XTIN
PH4/USB0PFLTBCBUS1
63
XTOUT
PH5BCBUS2
62
PH6BCBUS3
15
PH7SI/WUB
RESET#
14
RSTOUT#
PWREN#
PJ0
87
PJ1
39
PJ2
50
WAKEn
52
XOSC0 VCC
GND
53
XOSC1 VCC
GND
54
GNDVCCIOA
GND
55
VBATVCCIOB
GND
AGND
18pFRST
FT2232
ERBIAS
71
USB0DP AVCC
70
USB0DM
USB0RBIAS
73
USBID
4/15/2009
R3
R4
10K 10K
Released to production.
B
4/03/2009
Released for production.
24
23
22
21
20
19
17
16
15
13
12
11
10
40
39
38
37
36
35
33
32
30
29
28
27
26
41
R1
10K
PB2
PB3
PB4
PB5
PB6
PB7
B
C
R2
10K
1/21/2010
DC regulators U2 and U4 replaced for TI parts.
6/17/2011
Add option to install either LM3S9B90 or LM3S9D90
VIN
VOUT
R11
10K
5
LDO
C17
18pF
C12
4.7uF
1
4
16.000 MHz
PQ1LA333MSPQ
C16
18pF
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
R15
330
2
NR
C18
18pF
HIBn
WAKEn
VBAT
VCP_TX_SWO
TCK
TMS_SWDIO
TDI
TDO_SWO
VCP_TX_SWO
ETH_MDIO
ETH_TXON
ETH_TXOP
SWO_EN
PF4
20
18
16
14
12
10
8
6
4
2
DBG1
DBG2
USBPWR
USBFLT
PH5
PH6
PH7
3.3V
R5
10K
PJ0
PJ1
PJ2
3.3V
JTAG/SWD
WAKEn
3
42
14
31
AGND
D1
GREEN_LED
C13
PWR
0.1uF LM3S9B90/LM3S9D90
CVDD
CVDD
AVDD
D
D
C9
0.1uF9.1k
C3
0.1uF
R12
475USBDP
USBDM
C4
0.1uF
C5
0.1uF
XOSC1
C6
0.1uF
PA1
8
20
32
44
3.3V
56
68
81
R13
93
Y3
5VR
A
A
PB2
PB3
PB4
PB5
PB6
PB7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PF0
PF1
PF2
PF3
PF4
PF5
J1
10
8
6
4
2
BB
3.3V
9
7
5
PG1
3
PG7
1
VBUS
PH0
HDR 2X5-MH-SHRD
PH1
JTAG/SWD
PH2
PH5
PH6
PH7
3.3V
11
R19
VCP_TX
PD0
JR4
8
6
4
JR5
2
VCP_TX
12
VCP_RX
JR2
JR3 J2
PF3
C5
18pF
JR1
PB4
PF2
C4 4.194304 MHz
18pF
USR_PBn
7
USR_LED
5
DBG1
3
ETH_LED1
1
CC
JR6
ETH_LED0
HDR 2X4-MH-SHRD
PWR/UART
SRSTn
10
330
7
38
88
3
D2
GREEN_LED
FB1
DEBUG ACTIVE
C7
0.1uF
C8 U5D
C9
SN74LVC125A
0.1uF
0.1uF
C10
0.1uF
C11
0.1uF
C12
0.1uF
SW1
C14
0.1uF
C13
0.1uF
C6
1uF
TI
AECInstruments
- Austin
Texas
RESET
CVDD
C19
0.1uF
C20
0.1uF
108
108 Wild
Wild Basin
BasinRd.
Rd.
Suite
Suite 350
350
Austin,
Austin, TX
TX 78746
78746
C22
Designer:
Designer:
1uF
Arnaldo Cruz
Cruz
Drawing
Drawing Title:
Title:
Tempest,
Reset,
Test Pads
USB to JTAG,
SWD
Size
Size
Document
Document Number:
Number:
B
B
*
Date:
Date:
4
D
D
EK-LM3S9B90
and
EK-LM3S9D90
Evaluation Board
In Circuit Debug
Interface
(ICDI) Board
Page
Page Title:
Title:
Approved:
Approved:
July 5, 2011
5V
DBG2
VCP_RX
Arnaldo Cruz
Cruz
3
TP52
TP53
TP54
TP55
TP56
TP57
TP58
TP59
TP60
TP61
TP62
TP63
TP64
TP65
TP66
TP67
TP68
1M
C3
0.1uF
Drawn
Drawn by:
by:
22
TP35
TP36
TP37
TP38
TP39
TP40
TP41
TP42
TP43
TP44
TP45
TP46
TP47
TP48
TP49
TP50
TP51
PA0
VBAT
C23
0.1uF
11
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
XOSC0
46
R7
19
17
15 SRSTn
13 TDO
11
9 TCK
7 TMS
5 TDI
3
1
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PG0
PJ0
PJ1
PJ2
2X10 HDR-SHRD
5V
5V
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
SHDNn
J3
R9
SHDN
Y1
1
GND
PC4
PC5
PC6
PC7
DBGENn
DBGMOD
PF0
PF1
PF2
VCP_RX
PF3
PH0
PH1
PH2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
FT_SK
FT_DO
FT_DI
FT_CS
PD0
PD1
PD2 DBGRSTn
PD3
PD4
PD5
PD6 VSENSE
PD7
2
C15
18pF
64C8
9
GND
21
GND
45
GND
57
GND
69
GND
82
GND
3.3V
94
GND
U3
4
1
2/24/2009
R8
12.4K
5V
R14
HIB
45
33
C2
43
44
9
18
25
34
6.000MHz
10
CC
51
48
1
2
47
4
5
Y1
SW1
RESET
PA0/U0RX
PA1/U0TX
PA2/SSI0CLK
PA3/SSI0FSS
PA4/SSI0RX
PA5/SSI0TX
PA6
PA7
80
USBM
79
78
USBP
77
25
24
23
22
5V
DBG2
VCP_RX
VCP_TX
A
13
0.1uF
First release for prototypes.
4
C1
G2 26
27
28
29
30
31
34
35
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
2/24/2009
3
120ohm @ 100 MHz
J1
1
2
3
4
120ohm
5 @ 100 MHz
6
7
8
9
10
FB2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Description
A
U1
Description
Date
Date
1
3.3V
10K
10K
10K
10K VBUS
G4
G
Revision
Revision
120ohm @ 100 MHz
R1
R2
R3
FB1
R4
3
5V
1
A
A
2
G1
ID
5
5V
4
G3
3.3V
VBUS
J4 USB_MINI_B_RECEPTACLE
66
55
Rev
Rev
0001
0001
6/17/2011
5/18/2009
CB
Sheet
Sheet 11
of
of
22
66
22
JTAG/SWD Multiplexer
11
22
3
4
55
66
Revision History
PG0
PG1
XTALN
XTALP
PF5
PG7
19
18
17
16
41
40
37
36
OSCin
OSCout
48
49
R24
10K
3.3V
PG0
PG1
XTALNPHY
XTALPPHY
PF5
RXIP
RXIN
PG7
OSC0
OSC1
R6
10K
51
FT_DI
10
RSTn
33
C2
CC
64
0.1uF
HIB
RST
ERBIAS
GND
GND
GND
GND
GND
GND
GND
Y2
USB0DP
USB0DM
USB0RBIAS
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
CVDD
CVDD
Y1
1
2
4
C15
18pF
SWO_EN
16.000 MHz
C16
18pF
C17
18pF
C18
18pF
AGND
13
11
AVDD
LM3S9B90/LM3S9D90
D
D
TCK
8
R17
27
TDI
U4C
SN74LVC125A
PH0
PH1
PH2
3
R18
27
3.3V
6
3.3V
WAKEn
U6B
SN74LVC126A
8
R7
8
20
32
44
56
68
81
93
VCC
XOSC0
USBDP 9
USBDM
R9
C3
0.1uF
Y3
5
3.3V
C4 4.194304 MHz
18pF
VCC
U6E
SN74LVC126A
GND
JR1
VCP_RX
JR2
VCP_TX
PB4
JR3
PD0
JR4
C5
18pFC14
0.1uF
PF2
JR5
PF3
C15
0.1uF
JR6
C16
0.1uF
USR_PBn
CC
USR_LED
ETH_LED1
ETH_LED0
U4B
SN74LVC125A
C7
0.1uF
7
38
88
FB1
C8
0.1uF
C9
0.1uF
C10
0.1uF
C12
0.1uF
C13
0.1uF
C14
0.1uF
C6
1uF
11
12
C11
0.1uF
U6D
SN74LVC126A
TI AEC - Austin
CVDD
8
C19
0.1uF
9 C20
0.1uF
108 Wild Basin Rd.
Suite 350
Austin, TX 78746
C22
VCP_TX
Designer:
Drawing
Drawing Title:
Title:
Drawn by:
Page
Page Title:
Title:
Tempest,
Reset,
Test Pads
JTAG, SWD
Mux
Arnaldo Cruz
Size
Size
Document
Document Number:
Number:
B
Date:
Date:
4
D
D
EK-LM3S9B90
andInterface
EK-LM3S9D90
Evaluation Board
In Circuit Debug
(ICDI) Board
Arnaldo Cruz
1uF
*
July 5, 2011
VBUS
PH0
PH1
PH2
PH5
PH6
PH7
PA1
PA0
BB
3.3V
PG1
PG7
U5E
SN74LVC125A
VCC
1M
Approved:
3
PF0
PF1
PF2
PF3
PF4
PF5
TP52
TP53
TP54
TP55
TP56
TP57
TP58
TP59
TP60
TP61
TP62
TP63
TP64
TP65
TP66
TP67
TP68
GND
VBAT
U5C
SN74LVC125A
22
U4E
SN74LVC125A
GND
3.3V
C23
0.1uF
11
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
TDO_SWO
XOSC1
U6C
SN74LVC126A
6
TP35
TP36
TP37
TP38
TP39
TP40
TP41
TP42
TP43
TP44
TP45
TP46
TP47
TP48
TP49
TP50
TP51
R5
10K
5
9.1k
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PG0
PJ0
PJ1
PJ2
TMS_SWDIO
USBPWR
USBFLT
PH5
PH6
PH7
PJ0
PJ1
PJ2
A
A
PB2
PB3
PB4
PB5
PB6
PB7
SHDNn
ETH_MDIO
ETH_TXON
ETH_TXOP
U6A
SN74LVC126A
71
70
3
27
10
9
2
73
R16
PF4
86
PH0
85
PH1
84
PH2
83
PH3/USB0EPEN
76
PH4/USB0PFLT
63
2
PH5 3
62
PH6
15
PH7
R22
U4A
14 10K
PJ0
SN74LVC125A
87
PJ1
39
PJ2
50
WAKEn
52
XOSC0
53
XOSC1
54
GND
55
VBAT
LDO
25.000 MHz
PF0
PF1
PF2
PF3
Add option to install either LM3S9B90 or LM3S9D90
U4D
SN74LVC125A
R8
12.4K
9
21
45
57
69
82
94
1 VCP_TX_SWO
2
47
61
60
59
58
46
43
42
DC regulators U2 and U4 replaced for TI parts.
6/17/2011
4
4
3
2
1
SW1
PF0
PF1
PF2/LED1
PF3/LED0
MDIO
TXON
TXOP
PF4
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
12
1/21/2010
14
74
PE0
75
PE1
95
5
6
PE2
96
PE3
6
PE4
5
PE5
2 U5B
PE6
1 SN74LVC125A
PE7
10
11
12
13
97
98
99
100
C
5VR
TP1 TP18
FID2
FID3
TP2 40TP19
40 Mil Pad
Mil Pad
100 Mil Mask TP3 100
Mil Mask
TP20
TP4 TP21
TP5 TP22
TP6 TP23
TP7 TP24
TP8 Fiducials
TP25
TP9 TP26
PC4
TP10 TP27
PC5
TP11 TP28
PC6
TP12 TP29
PC7
TP13 TP30
TP14 TP31
HIBn
TP15 TP32
WAKEn
TP16 TP33
VBAT
TP17 TP34
7
HIBn
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PB2
PB3
PB4
PB5
PB6
PB7
5V
PA0
FID1 PA1
40 Mil Pad PA2
100 Mil Mask
PA3
PA4
PA5
PA6
PA7
14
3.3V
R23
Released to production.
14
DBG1
ETH_RXIP
ETH_RXIN
RESET
4/15/2009
13
7
5
3
1
HDR 2X4-MH-SHRD
PWR/UART
FT_CS
BB
B
USBID
10
8
6
4
2
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
R20
10K
10K
J2
DBG2
VCP_RX
VCP_TX
80
PC0/TCK/SWCLK
2
3
79
PC1/TMS/SWDIO
78
PC2/TDI
77
PC3/TDO/SWO
25 U5A
3.3V
PC4
24 SN74LVC125A
PC5
23
PC6
22
R21
PC7
66
67
72
65
92
91
90
89
Description
1
HDR 2X5-MH-SHRD
5V JTAG/SWD
DBGENn
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PB0/USB0ID
PB1/USB0VBUS
PB2/I2C0SCL
PB3/I2C0SDA
PB4
PB5
PB6
PB7
120ohm @ 100 MHz
0.1uF
2 TMS
4 TCK
6 TDO
DBGMOD
8 TDI
10 RSTn
PA0/U0RX
PA1/U0TX
PA2/SSI0CLK
PA3/SSI0FSS
PA4/SSI0RX
PA5/SSI0TX
PA6
PA7
1
C1
First release for prototypes.
4
J1
1
3
5
7
9
2/24/2009
10
3.3V
26
27
28
29
30
31
34
35
1
10K
10K
10K
10K
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
4
R1
R2
R3
R4
Date
A
U1
FT_DO
A
A
Revision
7
VBUS
7
FT_SK
55
Rev
Rev
CB
0001
0001
6/17/2011
4/9/2009
Sheet
Sheet 12
of
of
22
66
23
24
July 5, 2011
A P P E N D I X B
Connection Details
This appendix contains the following sections:
„
Component Locations (see page 25)
„
Board Dimensions (see page 26)
„
Board Connectivity (see page 27)
„
References (see page 27)
Component Locations
Figure B-1. EK-LM3S9B90 Evaluation Board Component Locations
Figure B-2. BD-ICDI Board Component Locations
July 5, 2011
25
Board Dimensions
Board Dimensions
Figure B-3. EK-LM3S9B90 Evaluation Board Dimensions
4.00
0.07
0.07
Ø 0.100
0.34
1.40
0.07
0.07
0.07
0.07
Figure B-4. In-Circuit Debug Interface Board Dimensions
2.50
0.07
0.07
Ø 0.100
1.40
0.07
0.07
26
0.07
July 5, 2011
Stellaris® LM3S9B90 Evaluation Kit User’s Manual
Board Connectivity
Figure B-5. ICDI – EK-LM3S9B90 Board Connectivity
8-wire cable
BD-ICDI
Board
PWR/UART
EK-LM3S9B90
Evaluation Board
JTAG/SWD
10-wire cable
References
In addition to this document, the following references are included on the Stellaris Evaluation Kit
CD-ROM and are also available for download at www.ti.com/stellaris:
„
Stellaris LM3S9B90 Data Sheet, publication DS-LM3S9B90
„
StellarisWare Driver Library
„
StellarisWare Driver Library User’s Manual, publication SW-DRL-UG
Additional references include:
„
FT2232D Dual USB/UART FIFO IC Datasheet, version 0.91, 2006, Future Technology
Devices International Ltd.
„
Information on development tool being used:
– RealView MDK web site, www.keil.com/arm/rvmdkkit.asp
– IAR Embedded Workbench web site, www.iar.com
– Sourcery CodeBench development tools web site,
www.codesourcery.com/gnu_toolchains/arm
– Code Red Technologies development tools web site, www.code-red-tech.com
– Texas Instruments’ Code Composer Studio™ IDE web site, www.ti.com/ccs
July 5, 2011
27
References
28
July 5, 2011
A P P E N D I X C
Microcontroller GPIO Assignments
The following table shows the LM3S9B90 GPIOs used by the EK-LM3S9B90 board. All other
GPIOs are available for use and accessible on the test pads.
Table C-1. EK-LM3S9B90 Evaluation Board GPIO Usage
Port
Function
Board Signal
PA0
U0RX
VCP_RX
Usage
Description
Virtual Communications port receive signal from J2
header. To disconnect from header cut JR1 jumper.
UART
PA1
U0TX
VCP_TX
PB0
USB0ID
USBID
PB1
USB0VBUS
VBUS
PB4
GPIO
USR_PBn
PC0
TCK/SWCLK
PC0
PC1
TMS/SWDIO
PC1
PC2
TDI
PC2
PC3
TDO/SWO
PC3
PD0
GPIO
USR_LED
PF2
LED1
ETH_LED1
Virtual Communications port transmit signal to J2
header. To disconnect from header cut JR2 jumper.
USBID signal from the USB-On-the-Go connector J5.
USB
User
USB VBUS input signal from USB-OTG connector J5 for
sensing VBUS levels.
Input from user pushbutton SW2. To disconnect from
pushbutton cut JR3 jumper.
JTAG or SWD clock input
JTAG/
SWD
JTAG TMS input or SWD bidirectional signal SWDIO
JTAG TDI signal input.
JTAG TDO output or SWD trace signal SWO output.
User
Output to user LED D2. To disconnect from LED cut JR4
jumper.
Output to RJ45 jack J6 yellow LED. To disconnect from
LED cut JR5 jumper.
Ethernet
PF3
PH3
LED0
USB0EPEN
ETH_LED0
Output to RJ45 jack J6 green LED. To disconnect from
LED cut JR6 jumper.
USBPWR
Output to USB-OTG power switch U3. When set high it
enables the USB-OTG power switch to provide USB
VBUS power to USB-OTG connector J5. When set low
power switch U3 is disabled.
USB
PH4
July 5, 2011
USB0PFLT
USBPFLT
Overcurrent input status from USB-OTG power switch
U3. When high the power switch status is normal. When
low an overcurrent condition has been detected by the
switch.
29
30
July 5, 2011
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