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Analyzer Reference
Sample Timing Diagrams
Sample Timing Diagrams
The following figures show examples of some events on the PCI bus, and
which states are detected by the PCI Analyzer in the various phases of
the event.
In the figures, the following abbreviations are used to identify the signals:
Table 17
Abbreviations used in Sample Timing Diagrams
Signal
Abbreviation
Meaning
b_state[]
i
Idle
A
Single address cycle
A1
First of a dual address cycle
A2
Second of a dual address cycle
d
Decoding
w
Wait
T
Transfer
S
Single phase
F
First data phase of the burst
M
Data phase within the burst
L
Last data phase of the burst
-
Invalid
n
No termination in this phase
MA
Master abort
C
Master completion
A
Target disconnectA
B
Target disconnectB
1
Target disconnect1
2
Target disconnect2
TA
Target abort.
burst[]
term[]
112
Agilent E2928A PCI Analyzer User’s Guide, August 2002