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8.5. ETM Trace Format
45
Table 8.6: ETM PIPESTAT encoding
Encoding
b000
Mnemonic
IE
b001
ID
b010
IN
b011
WT
b100
BE
b101
BD
b110
TR
b111
TD
Description
Instruction executed. An instruction executed but generated no associated
trace packet.
Instruction executed with data. A load or store executed and the data, address
or both
were placed into the FIFO.
Instruction not executed. An instruction didn’t execute because its condition
code test
failed.
Waitstate. No instruction executed and the pipeline didn’t advance, for example
because the memory system delayed an access or because the core executed an
internal cycle. A trace packet is output in this cycle.
Branch executed. An indirect branch executed, or a direct branch required the
branch address to be output.
Branch executed with data. A data access had ViewData enabled and loaded
the program counter.
Trigger. A trigger occurred and replaced the original PIPESTAT which is
output in TRACEPKT[2:0] instead. No other trace packet is output in this cycle.
Trace disabled. This PIPESTAT is output when TraceEnable is low or when
there is no trace packet to be output. In cycle accurate tracing TD is output
with TRACEPKT[0] high to indicate that TraceEnable was high.
Exceptions are traced as branches to the corresponding vector. Depending on the type of exception
this means that the current instruction was interrupted (Reset, IRQ, or FIQ) or executed and was then
turned into a branch to the exception vector (Prefetch Abort, Data Abort, Undefined Instruction or SWI).
Branch addresses and addresses of data accesses are output as up to five packets with the eighth bit
indicating that more packets follow (8th bit set). If less than five packets are output those bits that were
output replace the bits from the previous address. This means that after tracing started a full branch
address output is needed to acquire a complete 32 bit address. Earlier branches that output only part of
the address can’t be traced because the branch target address will be unknown.
32
J
Reason
[31:28] 1
16
24
[27:21]
1
[20:14]
8
1
[13:7]
0
1
[6:0]
The Reason given in a full branch address output provides further information about the branch. The
valid reason codes are given in table 8.7, other codes are reserved.
Following a branch two instructions that have already been fetched will have to be discarded, and
the pipeline needs to be refilled. Figure 8.8 shows how a branch was fetched, followed by fetching two
instructions (I+1 and I+2) from the current instruction stream. By the time the branch reached the execute
stage the destination of the branch is calculated and instruction I+2 is fetched, because at that point is
already too late to prevent the fetch. The branch instruction remains in the execute stage, the fetch and
decode stages are flushed, and a new instruction is fetched from the new location (N). In the next cycle
another instruction is fetched (N+1), the previously fetched instruction advances into the decode stage,