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2.6.1
2.6.1.1
Interrupt Latencies in Different States
Operating State
The ARM720T processor checks for a low level on its FIQ and IRQ inputs at the end of each instruction.
The interrupt latency is therefore directly related to the amount of time it takes to complete execution of
the current instruction when the interrupt condition is detected. First, there is a one to two clock cycle synchronization penalty. For the case where the EP7312 is operating at 13 MHz with a 16-bit external memory
system, and instruction sequence stored in one wait state FLASH memory, the worst-case interrupt latency
is 251 clock cycles. This includes a delay for cache line fills for instruction prefetches, and a data abort
occurring at the end of the LDM instruction, and the LDM being non-quad word aligned. In addition, the
worst-case interrupt latency assumes that LCD DMA cycles to support a panel size of 320 x 240 at 4 bitsper-pixel, 60 Hz refresh rate, is in progress.
This would give a worst-case interrupt latency of about 19.3 µs for the ARM720T processor operating at
13 MHz in this system. For those interrupt inputs which have de-glitching, this figure is increased by the
maximum time required to pass through the deglitcher, which is approximately 125 µs (2 cycle of the
16.384 kHz clock derived from the RTC oscillator). This would create an absolute worst-case latency of
approximately 141 µs. If the ARM720T is run at 36 MHz or greater and/or 32 bit wide external memory,
the 19.3 µs value will be reduced.
All the serial data transfer peripherals included in the EP7312 (except for the master-only SSI1) have local
buffering to ensure a reasonable interrupt latency response requirement for the OS of 1 ms or less. This
assumes that the design data rates do not exceed the data rates described in this specification. If the OS
cannot meet this requirement, there will be a risk of data over/underflow occurring.
2.6.1.2
Idle State
When leaving the Idle State as a result of an interrupt, the CPU clock is restarted after approximately two
clock cycles. However, there is still potentially up to 20 µs latency as described in the first section above,
unless the code is written to include at least two single cycle instructions immediately after the write to the
IDLE register (in which case the latency drops to a few microseconds).
This is important, as the Idle State can only be left because of a pending interrupt, which has to be synchronized by the processor before it can be serviced.
2.6.1.3
Standby State
The Standby State equates to the system being switched “off” (i.e., no display, and the main oscillator is
shut down). When the 18.432–73.72 MHz mode is selected, the PLL will be shut down. In the 13 MHz
mode, if the CLKENSL bit is set low, then the CLKEN signal will be forced low and can, if required, be
used to disable an external oscillator.
In the Standby State, all the system memory and state is maintained and the system time is kept up-to-date.
The PLL/on-chip oscillator or external oscillator is disabled and the system is static, except for the lowpower watch crystal (32 kHz) oscillator and divider chain to the RTC and LED flasher. The RUN signal
is driven low, therefore this signal can be used externally in the system to power down other system modules.
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