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2.15.2 ADC Interface — Master Mode Only SSI1 (Synchronous Serial Interface) ........... 43
2.15.3 Master / Slave SSI2 (Synchronous Serial Interface 2) .......................................... 44
2.15.3.1 Read Back of Residual Data ..................................................................... 46
2.15.3.2 Support for Asymmetric Traffic .................................................................. 46
2.15.3.3 Continuous Data Transfer ......................................................................... 47
2.15.3.4 Discontinuous Clock .................................................................................. 47
2.15.3.5 Error Conditions ......................................................................................... 47
2.15.3.6 Clock Polarity ............................................................................................. 47
2.16 LCD Controller with Support for On-Chip Frame Buffer .................................................. 48
2.17 Timer Counters ............................................................................................................... 50
2.17.1 Free Running Mode ............................................................................................... 50
2.17.2 Prescale Mode ....................................................................................................... 50
2.18 Real Time Clock .............................................................................................................. 50
2.18.1 Characteristics of the Real Time Clock Interface ................................................... 51
2.19 Dedicated LED Flasher ................................................................................................... 51
2.20 Two PWM Interfaces ....................................................................................................... 51
2.21 Boundary Scan ................................................................................................................ 52
2.22 In-Circuit Emulation ......................................................................................................... 53
2.22.1 Introduction ............................................................................................................ 53
2.22.2 Functionality ........................................................................................................... 53
2.23 Maximum-Configured EP7312-Based System ................................................................ 53
2.24 I/O Buffer Characteristics ................................................................................................ 55
3. TEST MODES ......................................................................................................................... 56
3.1 Oscillator and PLL Bypass Mode ...................................................................................... 56
3.2 Oscillator and PLL Test Mode ........................................................................................... 57
3.3 Debug / ICE Test Mode .................................................................................................... 58
3.4 Hi-Z (System) Test Mode ................................................................................................. 58
3.5 Software Selectable Test Functionality ............................................................................ 58
PART II: PIN AND REGISTER REFERENCE
4. PIN DESCRIPTIONS .............................................................................................................. 60
4.1 External Signal Functions ................................................................................................ 60
4.2 SSI / CODEC / DAI Pin Multiplexing ................................................................................ 66
4.3 Output Bi-Directional Pins .............................................................................................. 66
5. EP7312 MEMORY MAP ......................................................................................................... 67
6. REGISTER DESCRIPTIONS .................................................................................................. 68
6.1 Internal Registers .............................................................................................................. 68
6.1.1 PADR — Port A Data Register ................................................................................ 72
6.1.2 PBDR — Port B Data Register ................................................................................ 72
6.1.3 PDDR — Port D Data Register ................................................................................ 73
6.1.4 PADDR — Port A Data Direction Register .............................................................. 73
6.1.5 PBDDR — Port B Data Direction Register .............................................................. 73
6.1.6 PDDDR — Port D Data Direction Register .............................................................. 73
6.1.7 PEDR — Port E Data Register ................................................................................ 73
6.1.8 PEDDR — Port E Data Direction Register .............................................................. 73
6.2 System Control Registers ................................................................................................. 74
6.2.1 SYSCON1 — System Control Register 1 ................................................................ 74
6.2.2 SYSCON2— System Control Register 2 ................................................................. 77
6.2.3 SYSCON3 — System Control Register 3 ............................................................... 79
6.2.4 SYSFLG1 — System Status Flags Register ............................................................ 80
6.2.5 SYSFLG2 — System Status Register 2 .................................................................. 82
6.3 Interrupt Registers ............................................................................................................. 83
6.3.1 INTSR1 — Interrupt Status Register 1 .................................................................... 83
6.3.2 INTMR1 — Interrupt Mask Register 1 ..................................................................... 84
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DS508UM1