Download LH7A404 User`s Guide.book

List of Tables
Preface
Table 1. Register Name .......................................................................................... 0-xliii
Table 2. Bit Fields.................................................................................................... 0-xliii
Chapter 3 – Core and Data Paths
Table 3-1. Boot Mode Signals .................................................................................... 3-6
Table 3-2. AHB Blocks ............................................................................................... 3-9
Table 3-3. Clocking Mode Comparisons .................................................................. 3-11
Table 3-4. APB Peripheral Address Map ................................................................. 3-14
Chapter 4 – Boot ROM
Table 4-1. Boot Modes ............................................................................................... 4-2
Table 4-2. NAND Flash Electrical Connections.......................................................... 4-3
Table 4-3. Boot Log Memory Map.............................................................................. 4-5
Table 4-4. BOOTCLR Register .................................................................................. 4-6
Table 4-5. BOOTCLR Bit Fields ................................................................................. 4-6
Chapter 5 – Static Memory Controller (SMC)
Table 5-1. SMC Multiplexing ...................................................................................... 5-4
Table 5-2. PC Card Signal Multiplexing ..................................................................... 5-8
Table 5-3. SMC Memory Bank Selection ................................................................... 5-9
Table 5-4. PC Card Address Space ......................................................................... 5-10
Table 5-5. SMC Byte Lane Write Control ................................................................. 5-11
Table 5-6. PC Card Access Enable.......................................................................... 5-11
Table 5-7. SMC Memory Map .................................................................................. 5-17
Table 5-8. BCRx Registers....................................................................................... 5-18
Table 5-9. BCRx Fields ............................................................................................ 5-19
Table 5-10. PCxATTRIB Registers .......................................................................... 5-20
Table 5-11. PCxATTRIB Fields ................................................................................ 5-20
Table 5-12. PCxCOM Registers............................................................................... 5-21
Table 5-13. PCxCOM Fields .................................................................................... 5-21
Table 5-14. PCxIO Registers ................................................................................... 5-22
Table 5-15. PCxIO Fields ......................................................................................... 5-22
Table 5-16. PCMCIACON Register.......................................................................... 5-23
Table 5-17. PCMCIACON Fields.............................................................................. 5-23
Chapter 6 – Synchronous Dynamic Memory Controller
Table 6-1. SDMC Control Signals .............................................................................. 6-5
Table 6-2. SDRAM Clock Enable Multiplexing ........................................................... 6-6
Table 6-3. Address Line Multiplexing ......................................................................... 6-6
Table 6-4. Chip Select Address Coding ..................................................................... 6-8
Table 6-5. Memory System Examples ....................................................................... 6-9
Table 6-7. Address Mapping for 256 Mbit SDRAM .................................................. 6-10
Table 6-6. Synchronous Memory Address Decoding............................................... 6-10
Table 6-8. Address Ranges for 32-bit-wide Devices ................................................ 6-11
Table 6-9. Address Ranges for 16-bit-wide Devices ................................................ 6-13
NXP Semiconductors
Ver. 1.3 — 27 August 2007
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