Download ADMC331 Single Chip DSP Motor Controller

ADMC331–SPECIFICATIONS (V
Parameter
DD
= +5 V 10%, GND = SGND = 0 V, TA = –40C to +85C, unless otherwise noted)
Min
Typ
Max
Units
ANALOG-TO-DIGITAL CONVERTER
Signal Input
Resolution
Converter Linearity
Zero Offset
Channel-to-Channel Comparator Match
Comparator Delay
Current Source
Current Source Linearity
ELECTRICAL CHARACTERISTICS
VIL
Logic Low
VIH Logic High
VOL Low Level Output Voltage
VOL Low Level Output Voltage (XTAL)
VOH High Level Output Voltage
IIL
Low Level Input Current
IIH
High Level Input Current
IIH
Hi-Level PWMTRIP, PIO0–PIO23 Current
IIH
Hi-Level PWMPOL/PWMSR Current
IIL
Lo-Level PWMTRIP, PIO0–PIO23 Current
Lo-Level PWMPOL/PWMSR Current
IIL
IDD Supply Current (Dynamic)
IDD Supply Current (Idle)
REFERENCE VOLTAGE OUTPUT
Voltage Level
Output Voltage Change TMIN to TMAX
Conditions/Comments
Charging Capacitor = 1000 pF
2.5 kHz Sample Frequency
0.3
2
5
10.16
600
12.7
3.31
122
12
50
22
15.24
2
0.8
2
0.4
0.5
4
–10
10
100
10
10
100
120
60
2.2
16-BIT PWM TIMER
Counter Resolution
Edge Resolution (Single Update Mode)
Edge Resolution (Double Update Mode)
Programmable Deadtime Range
Programmable Deadtime Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
PWMSYNC Pulsewidth (TCRST)
Gate Drive Chop Frequency Range
0.198
0.077
0.02
AUXILIARY PWM TIMERS
Resolution
PWM Frequency
0.051
2.55
20
IOL = 2 mA
IOL = 2 mA
IOH = 0.5 mA
VIN = 0 V
VIN = VDD
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
13 MHz DSP Clock
13 MHz DSP Clock
100 µA Load
V
mV
16
9.8
6.5
Bits
ns
ns
µs
ns
µs
ns
kHz
µs
MHz
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
6.5
Bits
MHz
13 MHz CLKIN
78
76.9
0
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
mA
No Missing Codes
2.9
76.9
38.5
0
V
Bits
LSBs
mV
mV
ns
µA
%
78
76.9
8
NOTES
1
Signal input max V = 3.5 V if V DD = 5 V ± 5%.
2
Resolution varies with PWM switching frequency (13 MHz Clock in Double Update mode), 50.7 kHz = 9 bits, 6.3 kHz = 12 bits.
Specifications subject to change without notice.
–2–
REV. B