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Field Programmable Gate Array Registers
STAT
The Status Register (STAT) is a read only register. Reads of the unused
bits produce indeterminate values. Writes have no effect. Refer to Table 511.
Table 5-11. Bit Descriptions for the STAT Register
7 (most
significant
bit)
6
5
RES
FAL
DEG
4
ENUM
3
LM78
ALARM A
2
LM78
ALARM B
1
SMB
ALERT
0 (least
significant
bit)
MMC2
TEMP
ALARM
MMC2 TEMP ALARM (Bit 0)
This signal connects to the MMC2’s thermal sensor alarm output (ATF).
The input is latched when active. You can clear this bit (0) with a write to
the LTCLR register. A read of this bit returns the latched status of the
input.
SMB ALERT (Bit 1)
This bit reflects the level of the SMBus Alert signal.
LM78 ALARM A (Bit 3) and LM78 ALARM B (Bit 2)
The LM78 output functions feed these signals. The input is latched when
active. You can clear these bits (3 and 2) with a write to the LTCLR
register. A read of this bit returns the latched status of the input.
ENUM (Bit 4)
ENUM comes from the CompactPCI (CPCI) bus and signals the insertion
of a new device. The input is latched when active. You can clear this bit
(4) with a write to the LTCLR register. A read of this bit returns the latched
status of the input.
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