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ispGDX Process Flow
Creating a VHDL Test Bench from a Template
VHDL test stimulus can be specified either in the top-level HDL source or in a separate test bench (.vhd)
file. You can create the test bench manually using a text editor or use a VHDL Test Bench template (.vht)
file.
The easiest way to automatically create a VHDL Test Bench template is using the Project Navigator VHDL
Test Bench Template process. After the test bench template file is created, you must add your test stimulus
and rename it with the extension .vhd before importing it into your design.
To generate the VHDL test bench template and import it into your design:
1. Open your VHDL design in the Project Navigator.
2. In the Sources window, select the top-level VHDL design source (*.vhd) file.
Note: You can generate templates for lower-level modules. However, if you use these as test vector
templates you can only perform functional simulation and not timing simulation. The top test vector file
can perform both simulations.
3. In the Processes window, double-click the VHDL Test Bench Template process.
This process creates a template file for a VHDL Test Bench (<vhdl_sourcefile_name>.vht).
However, to use this file as a test bench in your design, you must edit it and rename it with the extension
.vhd.
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ispLEVER 4.0