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Download ADSP-2136x SHARC® Processor Hardware Reference
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Registers Reference 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 0 0 21 20 0 0 19 18 17 16 0 0 0 0 SRU_EXTMISCA3_INT IDP_DMA6_INT SRU_EXTMISCA2_INT IDP_DMA7_INT SRU_EXTMISCA1_INT SRC0_MUTE_INT SRU_EXTMISCA0_INT SRC1_MUTE_INT SRU_EXTMISCB5_INT SRC2_MUTE_INT SRU_EXTMISCB4_INT SRC3_MUTE_INT ISRU_EXTMISCB0_INT SRU_EXTMISCB3_INT ISRU_EXTMISCB2_INT ISRU_EXTMISCB1_INT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDP_DMA5_INT SPDIF_RX_VALID IDP_DMA4_INT SPDIF_RX_LOCK_START IDP_DMA3_INT SPDIF_RX_NO_STREAM IDP_DMA2_INT SPDIF_RX_CRC_ERROR IDP_DMA1_INT SPDIF_RX_NON_AUDIO IDP_DMA0_INT SPDIF_RX_EMPHASIS IDP_FIFO_OVR_INT SPDIF_RX_PARITY_ERROR IDP_FIFO_GTN_INT SPDIF_RX_CH_STAT_CHNG Figure A-58. DAI Interrupt Register Precision Clock Generator Registers The precision clock generator (PCG) consists of two identical units. Each of these two units (A and B) generates one clock (CLKA_O or CLKB_O) and one frame sync (FSA_O or FSB_O) output. These units can take an input clock signal from a crystal oscillator buffer output or any of the sources in group A of the signal routing unit. These signals are controlled by seven memory-mapped registers described in the following sections. ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21362/3/4/5/6 Processors A-117
