1
Download ADSP-2136x SHARC® Processor Hardware Reference
Transcript
Sony/Philips Digital Interface Registers DIRCTL (0x24A8) 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 23 22 0 0 21 20 0 0 19 18 17 16 0 0 0 0 0 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DIR_PLLDIS Disable PLL 0=Use derived clock from the digital PLL 1=Use clock input from external PLL DIR_MUTE Mute 0=Mute disabled 1=Mute serial data outputs, maintaining clocks (digital black) DIR_SCDF Single-Channel, Double-Frequency Mode Enable 0=2-channel mode disabled 1=2-channel mode enabled DIR_SCDF_LR Single-Channel, Double-Frequency Channel Select 0=Left channel 1=Right channel DIR_BIPHASE Parity Biphase Error Control 00=No action taken 01=Hold last valid sample 10=Replace invalid sample with zeros 11=Reserved DIR_LOCK Lock Error Control 00=No action taken 01=Hold last valid sample 10=Send zeros after the last valid sample 11=Soft mute of the last valid audio sample is performed Figure A-68. DIRCTL Register A-136 ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21362/3/4/5/6 Processors
