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System Hardware Principles FIGURE A-4: POWER MASTER/HEAD UNIT ECL SYSTEM TEST System Test Initiator asserts ECL Participants assert ECL PM starts up network NTSI = 3 ECL P1 P2 P3 P4 P5 PSync tSSEnd tTSI tTSI tTSI HU AuxIn Amp E1 O1 E2 O2 E3 O3 Emc Omc tTestPause tStartUp = 2.5 s t = 0.2xmc + 0.3 s System Test "Start Sequence" "Parameter Sequence" "Result Sequence" Figure A-5 depicts the same test; however, this time the Amp device did not respond (E3 = 1). This response implies that the Amp device does not have power, or the EHC on the Amp device is malfunctioning. The Head Unit reports no stable lock because the upstream device, Amp, is not functioning at all. FIGURE A-5: POWER MASTER ECL SYSTEM TEST – DEVICE FAILURE System Test Initiator asserts ECL Participants assert ECL PM starts up network NTSI = 3 ECL P1 P2 P3 P4 P5 PSync tSSEnd tTSI tTSI tTSI HU AuxIn Amp E1 O1 E2 O2 E3 O3 Emc Omc tTestPause tStartUp = 2.5 s t = 0.2xmc + 0.3 s System Test "Start Sequence" "Parameter Sequence" "Result Sequence" Figure A-6 depicts the same test; however, this time the AuxIn responds (E2 = 0) but indicates that stable lock was not achieved (O2 = 1). Although every device is showing its On bit high, this response implies a problem between the Head Unit and the AuxIn device (such as the network cable is broken or shorted to ground). Since the first device past the timing master, AuxIn, does not see stable lock, all down stream results can be ignored. FIGURE A-6: POWER MASTER ECL SYSTEM TEST – NETWORK FAILURE System Test Initiator asserts ECL Participants assert ECL PM starts up network NTSI = 3 ECL P1 P2 P3 P4 P5 PSync tSSEnd tTSI tTSI tTSI HU AuxIn Amp E1 O1 E2 O2 E3 O3 Emc Omc tTestPause tStartUp = 2.5 s t = 0.2xmc + 0.3 s System Test "Start Sequence" "Parameter Sequence" "Result Sequence" Figure A-7 illustrates an external test tool connected to the ECL line, where the ring is broken between the Head Unit and the AuxIn (the ECL response is the same as in Figure A-6). DS20005241A-page 32 2013 Microchip Technology Inc.
