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Chapter 6: XST Design Constraints
ROM_EXTRACT (ROM Extraction) ISE Design Suite Syntax Example
Define in ISE® Design Suite with:
Process > Properties > HDL Options > ROM Extraction.
ROM_STYLE (ROM Style)
ROM_STYLE (ROM Style) controls the way the macrogenerator implements the inferred ROM macros. ROM
Extraction (ROM_EXTRACT) must be set to yes in order to use ROM_STYLE.
ROM_STYLE values are:
•
auto (default)
•
block
The default is auto.
XST looks for the best implementation for each inferred ROM. The implementation style can be manually
forced to use block ROM or distributed ROM resources.
ROM_STYLE (ROM Style) Architecture Support
Applies to all FPGA devices. Does not apply to CPLD devices.
ROM_STYLE (ROM Style) Applicable Elements
Applies to the entire design, or to an entity, component, module, or signal.
ROM_STYLE (ROM Style) Propagation Rules
Applies to the entity, component, module, or signal to which it is attached.
ROM_STYLE (ROM Style) Syntax Examples
The following examples show how to use this constraint with particular tools or methods. If a tool or method
is not listed, you cannot use this constraint with it.
ROM_STYLE (ROM Style) VHDL Syntax Example
ROM Extraction (ROM_EXTRACT) must be set to yes in order to use ROM_STYLE.
Declare as follows:
attribute rom_style: string;
Specify as follows:
attribute rom_style of {signal_name | entity_name }: {signal | entity}
"{auto | block | distributed}";
is
The default is auto.
ROM_STYLE (ROM Style) Verilog Syntax Example
ROM Extraction (ROM_EXTRACT) must be set to yes in order to use ROM_STYLE.
Declare as follows:
(* rom_style = "{auto | block | distributed}" *)
The default is auto.
XST User Guide
UG627 (v 11.3) September 16, 2009
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